svd-generator 0.4.1

Converts device information from flattened device tree into an SVD description
Documentation 
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use crate::svd::{create_bit_range, create_field, create_register, create_register_properties};
use crate::Result;

/// Creates the Opencores PTC PWM v1 RPTC_CTRL register.
pub fn create() -> Result<svd::RegisterCluster> {
    Ok(svd::RegisterCluster::Register(create_register(
        "ctrl",
        "Opencores PTC PWM v1 RPTC_CTRL register control operation of PTC core.", 
        0xc,
        create_register_properties(9, 0)?,
        Some(&[
            create_field(
                "en",
                "When set, RPTC_CNTR can be incremented.",
                create_bit_range("[0:0]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "eclk",
                "When set, ptc_ecgt signal is used to increment RPTC_CNTR. When cleared, system clock is used instead.",
                create_bit_range("[1:1]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "nec",
                "When set, ptc_ecgt increments on negative edge and gates on low period. When cleared, ptc_ecgt increments on positive edge and gates on high period. This bit has effect only on `gating` function of ptc_ecgt when RPTC_CTRL[ECLK] bit is cleared.",
                create_bit_range("[2:2]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "oe",
                "Inverted value of this bit is reflected on the ptc_oen signal. It is used to enable PWM output driver.",
                create_bit_range("[3:3]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "single",
                "When set, RPTC_CNTR is not incremented anymore after it reaches value equal to the RPTC_LRC value. When cleared, RPTC_CNTR is restarted after it reaches value in the RPTC_LCR register.",
                create_bit_range("[4:4]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "inte",
                "When set, PTC asserts an interrupt when RPTC_CNTR value is equal to the value of RPTC_LRC or RPTC_HRC. When cleared, interrupts are masked.",
                create_bit_range("[5:5]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "int",
                "When read, this bit represents pending interrupt. When it is set, an interrupt is pending. When this bit is written with `1`, interrupt request is cleared.",
                create_bit_range("[6:6]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "cntrrst",
                "When set, RPTC_CNTR is under reset. When cleared, normal operation of the counter is allowed.",
                create_bit_range("[7:7]")?,
                svd::Access::ReadWrite,
                None,
            )?,
            create_field(
                "capte",
                "When set, ptc_capt signal can be used to capture RPTC_CNTR into RPTC_LRC or RPTC_HRC registers. Into which reference/capture register capture occurs depends on edge of the ptc_capt signal. When cleared, capture function is masked.",
                create_bit_range("[8:8]")?,
                svd::Access::ReadWrite,
                None,
            )?,
        ]),
        None,
    )?))
}