sv-parser 0.1.6

SystemVerilog parser library fully complient with IEEE 1800-2017
Documentation
[package]
name = "sv-parser"
version = "0.1.6"
authors = ["dalance@gmail.com"]
repository = "https://github.com/dalance/sv-parser"
keywords = ["parser", "verilog", "systemverilog"]
categories = ["parsing"]
license = "MIT OR Apache-2.0"
readme = "../README.md"
description = "SystemVerilog parser library fully complient with IEEE 1800-2017"
edition = "2018"

[features]
default = []
trace   = ["sv-parser-parser/trace"]

[dependencies]
nom                  = "5.0.0"
sv-parser-error      = {version = "0.1.0", path = "../sv-parser-error"}
sv-parser-parser     = {version = "0.1.0", path = "../sv-parser-parser"}
sv-parser-pp         = {version = "0.1.0", path = "../sv-parser-pp"}
sv-parser-syntaxtree = {version = "0.1.0", path = "../sv-parser-syntaxtree"}

[dev-dependencies]
structopt = "0.3.2"
criterion = "0.3"

[[bench]]
name = "parse_sv"
harness = false