sv-parser 0.1.6

[[bench]]
harness = false
name = "parse_sv"
[dependencies.nom]
version = "5.0.0"

[dependencies.sv-parser-error]
version = "0.1.0"

[dependencies.sv-parser-parser]
version = "0.1.0"

[dependencies.sv-parser-pp]
version = "0.1.0"

[dependencies.sv-parser-syntaxtree]
version = "0.1.0"
[dev-dependencies.criterion]
version = "0.3"

[dev-dependencies.structopt]
version = "0.3.2"

[features]
default = []
trace = ["sv-parser-parser/trace"]

[package]
authors = ["dalance@gmail.com"]
categories = ["parsing"]
description = "SystemVerilog parser library fully complient with IEEE 1800-2017"
edition = "2018"
keywords = ["parser", "verilog", "systemverilog"]
license = "MIT OR Apache-2.0"
name = "sv-parser"
readme = "../README.md"
repository = "https://github.com/dalance/sv-parser"
version = "0.1.6"