stm32wl/stm32wl5x_cm4/tim2/
af1.rs

1///Register `AF1` reader
2pub type R = crate::R<AF1rs>;
3///Register `AF1` writer
4pub type W = crate::W<AF1rs>;
5/**External trigger source selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum ETRSEL {
12    ///0: ETR legacy mode
13    Legacy = 0,
14    ///1: COMP1 output
15    Comp1 = 1,
16    ///2: COMP2 output
17    Comp2 = 2,
18}
19impl From<ETRSEL> for u8 {
20    #[inline(always)]
21    fn from(variant: ETRSEL) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for ETRSEL {
26    type Ux = u8;
27}
28impl crate::IsEnum for ETRSEL {}
29///Field `ETRSEL` reader - External trigger source selection
30pub type ETRSEL_R = crate::FieldReader<ETRSEL>;
31impl ETRSEL_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<ETRSEL> {
35        match self.bits {
36            0 => Some(ETRSEL::Legacy),
37            1 => Some(ETRSEL::Comp1),
38            2 => Some(ETRSEL::Comp2),
39            _ => None,
40        }
41    }
42    ///ETR legacy mode
43    #[inline(always)]
44    pub fn is_legacy(&self) -> bool {
45        *self == ETRSEL::Legacy
46    }
47    ///COMP1 output
48    #[inline(always)]
49    pub fn is_comp1(&self) -> bool {
50        *self == ETRSEL::Comp1
51    }
52    ///COMP2 output
53    #[inline(always)]
54    pub fn is_comp2(&self) -> bool {
55        *self == ETRSEL::Comp2
56    }
57}
58///Field `ETRSEL` writer - External trigger source selection
59pub type ETRSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ETRSEL>;
60impl<'a, REG> ETRSEL_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///ETR legacy mode
66    #[inline(always)]
67    pub fn legacy(self) -> &'a mut crate::W<REG> {
68        self.variant(ETRSEL::Legacy)
69    }
70    ///COMP1 output
71    #[inline(always)]
72    pub fn comp1(self) -> &'a mut crate::W<REG> {
73        self.variant(ETRSEL::Comp1)
74    }
75    ///COMP2 output
76    #[inline(always)]
77    pub fn comp2(self) -> &'a mut crate::W<REG> {
78        self.variant(ETRSEL::Comp2)
79    }
80}
81impl R {
82    ///Bits 14:17 - External trigger source selection
83    #[inline(always)]
84    pub fn etrsel(&self) -> ETRSEL_R {
85        ETRSEL_R::new(((self.bits >> 14) & 0x0f) as u8)
86    }
87}
88impl core::fmt::Debug for R {
89    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
90        f.debug_struct("AF1")
91            .field("etrsel", &self.etrsel())
92            .finish()
93    }
94}
95impl W {
96    ///Bits 14:17 - External trigger source selection
97    #[inline(always)]
98    pub fn etrsel(&mut self) -> ETRSEL_W<AF1rs> {
99        ETRSEL_W::new(self, 14)
100    }
101}
102/**TIM2 alternate function option register 1
103
104You can [`read`](crate::Reg::read) this register and get [`af1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`af1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
105
106See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WL5X_CM4.html#TIM2:AF1)*/
107pub struct AF1rs;
108impl crate::RegisterSpec for AF1rs {
109    type Ux = u32;
110}
111///`read()` method returns [`af1::R`](R) reader structure
112impl crate::Readable for AF1rs {}
113///`write(|w| ..)` method takes [`af1::W`](W) writer structure
114impl crate::Writable for AF1rs {
115    type Safety = crate::Unsafe;
116}
117///`reset()` method sets AF1 to value 0
118impl crate::Resettable for AF1rs {}
stm32wl/stm32wl5x_cm4/tim2/af1.rs

stm32wl/stm32wl5x_cm4/tim2/
af1.rs
