stm32wb/stm32wb55/rcc/
apb1enr1.rs

1///Register `APB1ENR1` reader
2pub type R = crate::R<APB1ENR1rs>;
3///Register `APB1ENR1` writer
4pub type W = crate::W<APB1ENR1rs>;
5/**CPU1 TIM2 timer clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM2EN {
11    ///0: Clock disabled
12    Disabled = 0,
13    ///1: Clock enabled
14    Enabled = 1,
15}
16impl From<TIM2EN> for bool {
17    #[inline(always)]
18    fn from(variant: TIM2EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TIM2EN` reader - CPU1 TIM2 timer clock enable
23pub type TIM2EN_R = crate::BitReader<TIM2EN>;
24impl TIM2EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> TIM2EN {
28        match self.bits {
29            false => TIM2EN::Disabled,
30            true => TIM2EN::Enabled,
31        }
32    }
33    ///Clock disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == TIM2EN::Disabled
37    }
38    ///Clock enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == TIM2EN::Enabled
42    }
43}
44///Field `TIM2EN` writer - CPU1 TIM2 timer clock enable
45pub type TIM2EN_W<'a, REG> = crate::BitWriter<'a, REG, TIM2EN>;
46impl<'a, REG> TIM2EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Clock disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(TIM2EN::Disabled)
54    }
55    ///Clock enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(TIM2EN::Enabled)
59    }
60}
61///Field `LCDEN` reader - CPU1 LCD clock enable
62pub use TIM2EN_R as LCDEN_R;
63///Field `RTCAPBEN` reader - CPU1 RTC APB clock enable
64pub use TIM2EN_R as RTCAPBEN_R;
65///Field `WWDGEN` reader - CPU1 Window watchdog clock enable
66pub use TIM2EN_R as WWDGEN_R;
67///Field `SPI2EN` reader - CPU1 SPI2 clock enable
68pub use TIM2EN_R as SPI2EN_R;
69///Field `I2C1EN` reader - CPU1 I2C1 clock enable
70pub use TIM2EN_R as I2C1EN_R;
71///Field `I2C3EN` reader - CPU1 I2C3 clock enable
72pub use TIM2EN_R as I2C3EN_R;
73///Field `CRSEN` reader - CPU1 CRS clock enable
74pub use TIM2EN_R as CRSEN_R;
75///Field `USBEN` reader - CPU1 USB clock enable
76pub use TIM2EN_R as USBEN_R;
77///Field `LPTIM1EN` reader - CPU1 Low power timer 1 clock enable
78pub use TIM2EN_R as LPTIM1EN_R;
79///Field `LCDEN` writer - CPU1 LCD clock enable
80pub use TIM2EN_W as LCDEN_W;
81///Field `RTCAPBEN` writer - CPU1 RTC APB clock enable
82pub use TIM2EN_W as RTCAPBEN_W;
83///Field `WWDGEN` writer - CPU1 Window watchdog clock enable
84pub use TIM2EN_W as WWDGEN_W;
85///Field `SPI2EN` writer - CPU1 SPI2 clock enable
86pub use TIM2EN_W as SPI2EN_W;
87///Field `I2C1EN` writer - CPU1 I2C1 clock enable
88pub use TIM2EN_W as I2C1EN_W;
89///Field `I2C3EN` writer - CPU1 I2C3 clock enable
90pub use TIM2EN_W as I2C3EN_W;
91///Field `CRSEN` writer - CPU1 CRS clock enable
92pub use TIM2EN_W as CRSEN_W;
93///Field `USBEN` writer - CPU1 USB clock enable
94pub use TIM2EN_W as USBEN_W;
95///Field `LPTIM1EN` writer - CPU1 Low power timer 1 clock enable
96pub use TIM2EN_W as LPTIM1EN_W;
97impl R {
98    ///Bit 0 - CPU1 TIM2 timer clock enable
99    #[inline(always)]
100    pub fn tim2en(&self) -> TIM2EN_R {
101        TIM2EN_R::new((self.bits & 1) != 0)
102    }
103    ///Bit 9 - CPU1 LCD clock enable
104    #[inline(always)]
105    pub fn lcden(&self) -> LCDEN_R {
106        LCDEN_R::new(((self.bits >> 9) & 1) != 0)
107    }
108    ///Bit 10 - CPU1 RTC APB clock enable
109    #[inline(always)]
110    pub fn rtcapben(&self) -> RTCAPBEN_R {
111        RTCAPBEN_R::new(((self.bits >> 10) & 1) != 0)
112    }
113    ///Bit 11 - CPU1 Window watchdog clock enable
114    #[inline(always)]
115    pub fn wwdgen(&self) -> WWDGEN_R {
116        WWDGEN_R::new(((self.bits >> 11) & 1) != 0)
117    }
118    ///Bit 14 - CPU1 SPI2 clock enable
119    #[inline(always)]
120    pub fn spi2en(&self) -> SPI2EN_R {
121        SPI2EN_R::new(((self.bits >> 14) & 1) != 0)
122    }
123    ///Bit 21 - CPU1 I2C1 clock enable
124    #[inline(always)]
125    pub fn i2c1en(&self) -> I2C1EN_R {
126        I2C1EN_R::new(((self.bits >> 21) & 1) != 0)
127    }
128    ///Bit 23 - CPU1 I2C3 clock enable
129    #[inline(always)]
130    pub fn i2c3en(&self) -> I2C3EN_R {
131        I2C3EN_R::new(((self.bits >> 23) & 1) != 0)
132    }
133    ///Bit 24 - CPU1 CRS clock enable
134    #[inline(always)]
135    pub fn crsen(&self) -> CRSEN_R {
136        CRSEN_R::new(((self.bits >> 24) & 1) != 0)
137    }
138    ///Bit 26 - CPU1 USB clock enable
139    #[inline(always)]
140    pub fn usben(&self) -> USBEN_R {
141        USBEN_R::new(((self.bits >> 26) & 1) != 0)
142    }
143    ///Bit 31 - CPU1 Low power timer 1 clock enable
144    #[inline(always)]
145    pub fn lptim1en(&self) -> LPTIM1EN_R {
146        LPTIM1EN_R::new(((self.bits >> 31) & 1) != 0)
147    }
148}
149impl core::fmt::Debug for R {
150    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
151        f.debug_struct("APB1ENR1")
152            .field("tim2en", &self.tim2en())
153            .field("lptim1en", &self.lptim1en())
154            .field("usben", &self.usben())
155            .field("crsen", &self.crsen())
156            .field("i2c3en", &self.i2c3en())
157            .field("i2c1en", &self.i2c1en())
158            .field("spi2en", &self.spi2en())
159            .field("wwdgen", &self.wwdgen())
160            .field("rtcapben", &self.rtcapben())
161            .field("lcden", &self.lcden())
162            .finish()
163    }
164}
165impl W {
166    ///Bit 0 - CPU1 TIM2 timer clock enable
167    #[inline(always)]
168    pub fn tim2en(&mut self) -> TIM2EN_W<APB1ENR1rs> {
169        TIM2EN_W::new(self, 0)
170    }
171    ///Bit 9 - CPU1 LCD clock enable
172    #[inline(always)]
173    pub fn lcden(&mut self) -> LCDEN_W<APB1ENR1rs> {
174        LCDEN_W::new(self, 9)
175    }
176    ///Bit 10 - CPU1 RTC APB clock enable
177    #[inline(always)]
178    pub fn rtcapben(&mut self) -> RTCAPBEN_W<APB1ENR1rs> {
179        RTCAPBEN_W::new(self, 10)
180    }
181    ///Bit 11 - CPU1 Window watchdog clock enable
182    #[inline(always)]
183    pub fn wwdgen(&mut self) -> WWDGEN_W<APB1ENR1rs> {
184        WWDGEN_W::new(self, 11)
185    }
186    ///Bit 14 - CPU1 SPI2 clock enable
187    #[inline(always)]
188    pub fn spi2en(&mut self) -> SPI2EN_W<APB1ENR1rs> {
189        SPI2EN_W::new(self, 14)
190    }
191    ///Bit 21 - CPU1 I2C1 clock enable
192    #[inline(always)]
193    pub fn i2c1en(&mut self) -> I2C1EN_W<APB1ENR1rs> {
194        I2C1EN_W::new(self, 21)
195    }
196    ///Bit 23 - CPU1 I2C3 clock enable
197    #[inline(always)]
198    pub fn i2c3en(&mut self) -> I2C3EN_W<APB1ENR1rs> {
199        I2C3EN_W::new(self, 23)
200    }
201    ///Bit 24 - CPU1 CRS clock enable
202    #[inline(always)]
203    pub fn crsen(&mut self) -> CRSEN_W<APB1ENR1rs> {
204        CRSEN_W::new(self, 24)
205    }
206    ///Bit 26 - CPU1 USB clock enable
207    #[inline(always)]
208    pub fn usben(&mut self) -> USBEN_W<APB1ENR1rs> {
209        USBEN_W::new(self, 26)
210    }
211    ///Bit 31 - CPU1 Low power timer 1 clock enable
212    #[inline(always)]
213    pub fn lptim1en(&mut self) -> LPTIM1EN_W<APB1ENR1rs> {
214        LPTIM1EN_W::new(self, 31)
215    }
216}
217/**APB1ENR1
218
219You can [`read`](crate::Reg::read) this register and get [`apb1enr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
220
221See register [structure](https://stm32-rs.github.io/stm32-rs/STM32WB55.html#RCC:APB1ENR1)*/
222pub struct APB1ENR1rs;
223impl crate::RegisterSpec for APB1ENR1rs {
224    type Ux = u32;
225}
226///`read()` method returns [`apb1enr1::R`](R) reader structure
227impl crate::Readable for APB1ENR1rs {}
228///`write(|w| ..)` method takes [`apb1enr1::W`](W) writer structure
229impl crate::Writable for APB1ENR1rs {
230    type Safety = crate::Unsafe;
231}
232///`reset()` method sets APB1ENR1 to value 0x0400
233impl crate::Resettable for APB1ENR1rs {
234    const RESET_VALUE: u32 = 0x0400;
235}
stm32wb/stm32wb55/rcc/apb1enr1.rs

stm32wb/stm32wb55/rcc/
apb1enr1.rs
