#[repr(C)]pub struct RegisterBlock {}Expand description
Register block
Fields§
§cr1: CR10x00 - control register 1
cr2: CR20x04 - control register 2
smcr: SMCR0x08 - slave mode control register
dier: DIER0x0c - DMA/Interrupt enable register
sr: SR0x10 - status register
egr: EGR0x14 - event generation register
ccer: CCER0x20 - capture/compare enable register
cnt: CNT0x24 - counter
psc: PSC0x28 - prescaler
arr: ARR0x2c - auto-reload register
ccr1: CCR10x34 - capture/compare register 1
ccr2: CCR20x38 - capture/compare register 2
ccr3: CCR30x3c - capture/compare register 3
ccr4: CCR40x40 - capture/compare register 4
dcr: DCR0x48 - DMA control register
dmar: DMAR0x4c - DMA address for full transfer
or: OR0x50 - TIM2 option register
af: AF0x60 - TIM2 alternate function option register 1
Implementations§
Source§impl RegisterBlock
impl RegisterBlock
Sourcepub fn ccmr1_input(&self) -> &CCMR1_INPUT
pub fn ccmr1_input(&self) -> &CCMR1_INPUT
0x18 - capture/compare mode register 1 (input mode)
Sourcepub fn ccmr1_input_mut(&self) -> &mut CCMR1_INPUT
pub fn ccmr1_input_mut(&self) -> &mut CCMR1_INPUT
0x18 - capture/compare mode register 1 (input mode)
Sourcepub fn ccmr1_output(&self) -> &CCMR1_OUTPUT
pub fn ccmr1_output(&self) -> &CCMR1_OUTPUT
0x18 - capture/compare mode register 1 (output mode)
Sourcepub fn ccmr1_output_mut(&self) -> &mut CCMR1_OUTPUT
pub fn ccmr1_output_mut(&self) -> &mut CCMR1_OUTPUT
0x18 - capture/compare mode register 1 (output mode)
Sourcepub fn ccmr2_input(&self) -> &CCMR2_INPUT
pub fn ccmr2_input(&self) -> &CCMR2_INPUT
0x1c - capture/compare mode register 2 (input mode)
Sourcepub fn ccmr2_input_mut(&self) -> &mut CCMR2_INPUT
pub fn ccmr2_input_mut(&self) -> &mut CCMR2_INPUT
0x1c - capture/compare mode register 2 (input mode)
Sourcepub fn ccmr2_output(&self) -> &CCMR2_OUTPUT
pub fn ccmr2_output(&self) -> &CCMR2_OUTPUT
0x1c - capture/compare mode register 2 (output mode)
Sourcepub fn ccmr2_output_mut(&self) -> &mut CCMR2_OUTPUT
pub fn ccmr2_output_mut(&self) -> &mut CCMR2_OUTPUT
0x1c - capture/compare mode register 2 (output mode)