stm32wb_pac/tim2/
egr.rs

1#[doc = "Writer for register EGR"]
2pub type W = crate::W<u32, super::EGR>;
3#[doc = "Register EGR `reset()`'s with value 0"]
4impl crate::ResetValue for super::EGR {
5    type Type = u32;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `TG`"]
12pub struct TG_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> TG_W<'a> {
16    #[doc = r"Sets the field bit"]
17    #[inline(always)]
18    pub fn set_bit(self) -> &'a mut W {
19        self.bit(true)
20    }
21    #[doc = r"Clears the field bit"]
22    #[inline(always)]
23    pub fn clear_bit(self) -> &'a mut W {
24        self.bit(false)
25    }
26    #[doc = r"Writes raw bits to the field"]
27    #[inline(always)]
28    pub fn bit(self, value: bool) -> &'a mut W {
29        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
30        self.w
31    }
32}
33#[doc = "Write proxy for field `CC4G`"]
34pub struct CC4G_W<'a> {
35    w: &'a mut W,
36}
37impl<'a> CC4G_W<'a> {
38    #[doc = r"Sets the field bit"]
39    #[inline(always)]
40    pub fn set_bit(self) -> &'a mut W {
41        self.bit(true)
42    }
43    #[doc = r"Clears the field bit"]
44    #[inline(always)]
45    pub fn clear_bit(self) -> &'a mut W {
46        self.bit(false)
47    }
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub fn bit(self, value: bool) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
52        self.w
53    }
54}
55#[doc = "Write proxy for field `CC3G`"]
56pub struct CC3G_W<'a> {
57    w: &'a mut W,
58}
59impl<'a> CC3G_W<'a> {
60    #[doc = r"Sets the field bit"]
61    #[inline(always)]
62    pub fn set_bit(self) -> &'a mut W {
63        self.bit(true)
64    }
65    #[doc = r"Clears the field bit"]
66    #[inline(always)]
67    pub fn clear_bit(self) -> &'a mut W {
68        self.bit(false)
69    }
70    #[doc = r"Writes raw bits to the field"]
71    #[inline(always)]
72    pub fn bit(self, value: bool) -> &'a mut W {
73        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
74        self.w
75    }
76}
77#[doc = "Write proxy for field `CC2G`"]
78pub struct CC2G_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> CC2G_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
96        self.w
97    }
98}
99#[doc = "Write proxy for field `CC1G`"]
100pub struct CC1G_W<'a> {
101    w: &'a mut W,
102}
103impl<'a> CC1G_W<'a> {
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
118        self.w
119    }
120}
121#[doc = "Write proxy for field `UG`"]
122pub struct UG_W<'a> {
123    w: &'a mut W,
124}
125impl<'a> UG_W<'a> {
126    #[doc = r"Sets the field bit"]
127    #[inline(always)]
128    pub fn set_bit(self) -> &'a mut W {
129        self.bit(true)
130    }
131    #[doc = r"Clears the field bit"]
132    #[inline(always)]
133    pub fn clear_bit(self) -> &'a mut W {
134        self.bit(false)
135    }
136    #[doc = r"Writes raw bits to the field"]
137    #[inline(always)]
138    pub fn bit(self, value: bool) -> &'a mut W {
139        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
140        self.w
141    }
142}
143impl W {
144    #[doc = "Bit 6 - Trigger generation"]
145    #[inline(always)]
146    pub fn tg(&mut self) -> TG_W {
147        TG_W { w: self }
148    }
149    #[doc = "Bit 4 - Capture/compare 4 generation"]
150    #[inline(always)]
151    pub fn cc4g(&mut self) -> CC4G_W {
152        CC4G_W { w: self }
153    }
154    #[doc = "Bit 3 - Capture/compare 3 generation"]
155    #[inline(always)]
156    pub fn cc3g(&mut self) -> CC3G_W {
157        CC3G_W { w: self }
158    }
159    #[doc = "Bit 2 - Capture/compare 2 generation"]
160    #[inline(always)]
161    pub fn cc2g(&mut self) -> CC2G_W {
162        CC2G_W { w: self }
163    }
164    #[doc = "Bit 1 - Capture/compare 1 generation"]
165    #[inline(always)]
166    pub fn cc1g(&mut self) -> CC1G_W {
167        CC1G_W { w: self }
168    }
169    #[doc = "Bit 0 - Update generation"]
170    #[inline(always)]
171    pub fn ug(&mut self) -> UG_W {
172        UG_W { w: self }
173    }
174}
stm32wb_pac/tim2/egr.rs

stm32wb_pac/tim2/
egr.rs
