stm32wb_pac/tim17/
egr.rs

1#[doc = "Writer for register EGR"]
2pub type W = crate::W<u32, super::EGR>;
3#[doc = "Register EGR `reset()`'s with value 0"]
4impl crate::ResetValue for super::EGR {
5    type Type = u32;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `BG`"]
12pub struct BG_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> BG_W<'a> {
16    #[doc = r"Sets the field bit"]
17    #[inline(always)]
18    pub fn set_bit(self) -> &'a mut W {
19        self.bit(true)
20    }
21    #[doc = r"Clears the field bit"]
22    #[inline(always)]
23    pub fn clear_bit(self) -> &'a mut W {
24        self.bit(false)
25    }
26    #[doc = r"Writes raw bits to the field"]
27    #[inline(always)]
28    pub fn bit(self, value: bool) -> &'a mut W {
29        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
30        self.w
31    }
32}
33#[doc = "Write proxy for field `TG`"]
34pub struct TG_W<'a> {
35    w: &'a mut W,
36}
37impl<'a> TG_W<'a> {
38    #[doc = r"Sets the field bit"]
39    #[inline(always)]
40    pub fn set_bit(self) -> &'a mut W {
41        self.bit(true)
42    }
43    #[doc = r"Clears the field bit"]
44    #[inline(always)]
45    pub fn clear_bit(self) -> &'a mut W {
46        self.bit(false)
47    }
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub fn bit(self, value: bool) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
52        self.w
53    }
54}
55#[doc = "Write proxy for field `COMG`"]
56pub struct COMG_W<'a> {
57    w: &'a mut W,
58}
59impl<'a> COMG_W<'a> {
60    #[doc = r"Sets the field bit"]
61    #[inline(always)]
62    pub fn set_bit(self) -> &'a mut W {
63        self.bit(true)
64    }
65    #[doc = r"Clears the field bit"]
66    #[inline(always)]
67    pub fn clear_bit(self) -> &'a mut W {
68        self.bit(false)
69    }
70    #[doc = r"Writes raw bits to the field"]
71    #[inline(always)]
72    pub fn bit(self, value: bool) -> &'a mut W {
73        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
74        self.w
75    }
76}
77#[doc = "Write proxy for field `CC1G`"]
78pub struct CC1G_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> CC1G_W<'a> {
82    #[doc = r"Sets the field bit"]
83    #[inline(always)]
84    pub fn set_bit(self) -> &'a mut W {
85        self.bit(true)
86    }
87    #[doc = r"Clears the field bit"]
88    #[inline(always)]
89    pub fn clear_bit(self) -> &'a mut W {
90        self.bit(false)
91    }
92    #[doc = r"Writes raw bits to the field"]
93    #[inline(always)]
94    pub fn bit(self, value: bool) -> &'a mut W {
95        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
96        self.w
97    }
98}
99#[doc = "Write proxy for field `UG`"]
100pub struct UG_W<'a> {
101    w: &'a mut W,
102}
103impl<'a> UG_W<'a> {
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
118        self.w
119    }
120}
121impl W {
122    #[doc = "Bit 7 - Break generation"]
123    #[inline(always)]
124    pub fn bg(&mut self) -> BG_W {
125        BG_W { w: self }
126    }
127    #[doc = "Bit 6 - Trigger generation"]
128    #[inline(always)]
129    pub fn tg(&mut self) -> TG_W {
130        TG_W { w: self }
131    }
132    #[doc = "Bit 5 - Capture/Compare control update generation"]
133    #[inline(always)]
134    pub fn comg(&mut self) -> COMG_W {
135        COMG_W { w: self }
136    }
137    #[doc = "Bit 1 - Capture/compare 1 generation"]
138    #[inline(always)]
139    pub fn cc1g(&mut self) -> CC1G_W {
140        CC1G_W { w: self }
141    }
142    #[doc = "Bit 0 - Update generation"]
143    #[inline(always)]
144    pub fn ug(&mut self) -> UG_W {
145        UG_W { w: self }
146    }
147}
stm32wb_pac/tim17/egr.rs

stm32wb_pac/tim17/
egr.rs
