stm32wb_pac/tim17/
dmar.rs

1#[doc = "Reader of register DMAR"]
2pub type R = crate::R<u32, super::DMAR>;
3#[doc = "Writer for register DMAR"]
4pub type W = crate::W<u32, super::DMAR>;
5#[doc = "Register DMAR `reset()`'s with value 0"]
6impl crate::ResetValue for super::DMAR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DMAB`"]
14pub type DMAB_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `DMAB`"]
16pub struct DMAB_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DMAB_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:15 - DMA register for burst accesses"]
29    #[inline(always)]
30    pub fn dmab(&self) -> DMAB_R {
31        DMAB_R::new((self.bits & 0xffff) as u16)
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - DMA register for burst accesses"]
36    #[inline(always)]
37    pub fn dmab(&mut self) -> DMAB_W {
38        DMAB_W { w: self }
39    }
40}
stm32wb_pac/tim17/dmar.rs

stm32wb_pac/tim17/
dmar.rs
