stm32wb_pac/syscfg/
exticr2.rs

1#[doc = "Reader of register EXTICR2"]
2pub type R = crate::R<u32, super::EXTICR2>;
3#[doc = "Writer for register EXTICR2"]
4pub type W = crate::W<u32, super::EXTICR2>;
5#[doc = "Register EXTICR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::EXTICR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `EXTI7`"]
14pub type EXTI7_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `EXTI7`"]
16pub struct EXTI7_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> EXTI7_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u32) & 0x07) << 12);
24        self.w
25    }
26}
27#[doc = "Reader of field `EXTI6`"]
28pub type EXTI6_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `EXTI6`"]
30pub struct EXTI6_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> EXTI6_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
38        self.w
39    }
40}
41#[doc = "Reader of field `EXTI5`"]
42pub type EXTI5_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `EXTI5`"]
44pub struct EXTI5_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> EXTI5_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
52        self.w
53    }
54}
55#[doc = "Reader of field `EXTI4`"]
56pub type EXTI4_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `EXTI4`"]
58pub struct EXTI4_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> EXTI4_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
66        self.w
67    }
68}
69impl R {
70    #[doc = "Bits 12:14 - EXTI 7 configuration bits"]
71    #[inline(always)]
72    pub fn exti7(&self) -> EXTI7_R {
73        EXTI7_R::new(((self.bits >> 12) & 0x07) as u8)
74    }
75    #[doc = "Bits 8:10 - EXTI 6 configuration bits"]
76    #[inline(always)]
77    pub fn exti6(&self) -> EXTI6_R {
78        EXTI6_R::new(((self.bits >> 8) & 0x07) as u8)
79    }
80    #[doc = "Bits 4:6 - EXTI 5 configuration bits"]
81    #[inline(always)]
82    pub fn exti5(&self) -> EXTI5_R {
83        EXTI5_R::new(((self.bits >> 4) & 0x07) as u8)
84    }
85    #[doc = "Bits 0:2 - EXTI 4 configuration bits"]
86    #[inline(always)]
87    pub fn exti4(&self) -> EXTI4_R {
88        EXTI4_R::new((self.bits & 0x07) as u8)
89    }
90}
91impl W {
92    #[doc = "Bits 12:14 - EXTI 7 configuration bits"]
93    #[inline(always)]
94    pub fn exti7(&mut self) -> EXTI7_W {
95        EXTI7_W { w: self }
96    }
97    #[doc = "Bits 8:10 - EXTI 6 configuration bits"]
98    #[inline(always)]
99    pub fn exti6(&mut self) -> EXTI6_W {
100        EXTI6_W { w: self }
101    }
102    #[doc = "Bits 4:6 - EXTI 5 configuration bits"]
103    #[inline(always)]
104    pub fn exti5(&mut self) -> EXTI5_W {
105        EXTI5_W { w: self }
106    }
107    #[doc = "Bits 0:2 - EXTI 4 configuration bits"]
108    #[inline(always)]
109    pub fn exti4(&mut self) -> EXTI4_W {
110        EXTI4_W { w: self }
111    }
112}
stm32wb_pac/syscfg/exticr2.rs

stm32wb_pac/syscfg/
exticr2.rs
