stm32wb_pac/syscfg/
cfgr2.rs

1#[doc = "Reader of register CFGR2"]
2pub type R = crate::R<u32, super::CFGR2>;
3#[doc = "Writer for register CFGR2"]
4pub type W = crate::W<u32, super::CFGR2>;
5#[doc = "Register CFGR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::CFGR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `SPF`"]
14pub type SPF_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `SPF`"]
16pub struct SPF_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> SPF_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
34        self.w
35    }
36}
37#[doc = "Write proxy for field `ECCL`"]
38pub struct ECCL_W<'a> {
39    w: &'a mut W,
40}
41impl<'a> ECCL_W<'a> {
42    #[doc = r"Sets the field bit"]
43    #[inline(always)]
44    pub fn set_bit(self) -> &'a mut W {
45        self.bit(true)
46    }
47    #[doc = r"Clears the field bit"]
48    #[inline(always)]
49    pub fn clear_bit(self) -> &'a mut W {
50        self.bit(false)
51    }
52    #[doc = r"Writes raw bits to the field"]
53    #[inline(always)]
54    pub fn bit(self, value: bool) -> &'a mut W {
55        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
56        self.w
57    }
58}
59#[doc = "Write proxy for field `PVDL`"]
60pub struct PVDL_W<'a> {
61    w: &'a mut W,
62}
63impl<'a> PVDL_W<'a> {
64    #[doc = r"Sets the field bit"]
65    #[inline(always)]
66    pub fn set_bit(self) -> &'a mut W {
67        self.bit(true)
68    }
69    #[doc = r"Clears the field bit"]
70    #[inline(always)]
71    pub fn clear_bit(self) -> &'a mut W {
72        self.bit(false)
73    }
74    #[doc = r"Writes raw bits to the field"]
75    #[inline(always)]
76    pub fn bit(self, value: bool) -> &'a mut W {
77        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
78        self.w
79    }
80}
81#[doc = "Write proxy for field `SPL`"]
82pub struct SPL_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> SPL_W<'a> {
86    #[doc = r"Sets the field bit"]
87    #[inline(always)]
88    pub fn set_bit(self) -> &'a mut W {
89        self.bit(true)
90    }
91    #[doc = r"Clears the field bit"]
92    #[inline(always)]
93    pub fn clear_bit(self) -> &'a mut W {
94        self.bit(false)
95    }
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub fn bit(self, value: bool) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
100        self.w
101    }
102}
103#[doc = "Write proxy for field `CLL`"]
104pub struct CLL_W<'a> {
105    w: &'a mut W,
106}
107impl<'a> CLL_W<'a> {
108    #[doc = r"Sets the field bit"]
109    #[inline(always)]
110    pub fn set_bit(self) -> &'a mut W {
111        self.bit(true)
112    }
113    #[doc = r"Clears the field bit"]
114    #[inline(always)]
115    pub fn clear_bit(self) -> &'a mut W {
116        self.bit(false)
117    }
118    #[doc = r"Writes raw bits to the field"]
119    #[inline(always)]
120    pub fn bit(self, value: bool) -> &'a mut W {
121        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
122        self.w
123    }
124}
125impl R {
126    #[doc = "Bit 8 - SRAM2 parity error flag"]
127    #[inline(always)]
128    pub fn spf(&self) -> SPF_R {
129        SPF_R::new(((self.bits >> 8) & 0x01) != 0)
130    }
131}
132impl W {
133    #[doc = "Bit 8 - SRAM2 parity error flag"]
134    #[inline(always)]
135    pub fn spf(&mut self) -> SPF_W {
136        SPF_W { w: self }
137    }
138    #[doc = "Bit 3 - ECC Lock"]
139    #[inline(always)]
140    pub fn eccl(&mut self) -> ECCL_W {
141        ECCL_W { w: self }
142    }
143    #[doc = "Bit 2 - PVD lock enable bit"]
144    #[inline(always)]
145    pub fn pvdl(&mut self) -> PVDL_W {
146        PVDL_W { w: self }
147    }
148    #[doc = "Bit 1 - SRAM2 parity lock bit"]
149    #[inline(always)]
150    pub fn spl(&mut self) -> SPL_W {
151        SPL_W { w: self }
152    }
153    #[doc = "Bit 0 - Cortex-M4 LOCKUP (Hardfault) output enable bit"]
154    #[inline(always)]
155    pub fn cll(&mut self) -> CLL_W {
156        CLL_W { w: self }
157    }
158}
stm32wb_pac/syscfg/cfgr2.rs

stm32wb_pac/syscfg/
cfgr2.rs
