stm32wb_pac/syscfg/
c2imr2.rs

1#[doc = "Reader of register C2IMR2"]
2pub type R = crate::R<u32, super::C2IMR2>;
3#[doc = "Writer for register C2IMR2"]
4pub type W = crate::W<u32, super::C2IMR2>;
5#[doc = "Register C2IMR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::C2IMR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DMA1_CH1_IM`"]
14pub type DMA1_CH1_IM_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DMA1_CH1_IM`"]
16pub struct DMA1_CH1_IM_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DMA1_CH1_IM_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `DMA1_CH2_IM`"]
38pub type DMA1_CH2_IM_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DMA1_CH2_IM`"]
40pub struct DMA1_CH2_IM_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> DMA1_CH2_IM_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `DMA1_CH3_IM`"]
62pub type DMA1_CH3_IM_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `DMA1_CH3_IM`"]
64pub struct DMA1_CH3_IM_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> DMA1_CH3_IM_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Reader of field `DMA1_CH4_IM`"]
86pub type DMA1_CH4_IM_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DMA1_CH4_IM`"]
88pub struct DMA1_CH4_IM_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DMA1_CH4_IM_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106        self.w
107    }
108}
109#[doc = "Reader of field `DMA1_CH5_IM`"]
110pub type DMA1_CH5_IM_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `DMA1_CH5_IM`"]
112pub struct DMA1_CH5_IM_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> DMA1_CH5_IM_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130        self.w
131    }
132}
133#[doc = "Reader of field `DMA1_CH6_IM`"]
134pub type DMA1_CH6_IM_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `DMA1_CH6_IM`"]
136pub struct DMA1_CH6_IM_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> DMA1_CH6_IM_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154        self.w
155    }
156}
157#[doc = "Reader of field `DMA1_CH7_IM`"]
158pub type DMA1_CH7_IM_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `DMA1_CH7_IM`"]
160pub struct DMA1_CH7_IM_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DMA1_CH7_IM_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
178        self.w
179    }
180}
181#[doc = "Reader of field `DMA2_CH1_IM`"]
182pub type DMA2_CH1_IM_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `DMA2_CH1_IM`"]
184pub struct DMA2_CH1_IM_W<'a> {
185    w: &'a mut W,
186}
187impl<'a> DMA2_CH1_IM_W<'a> {
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
202        self.w
203    }
204}
205#[doc = "Reader of field `DMA2_CH2_IM`"]
206pub type DMA2_CH2_IM_R = crate::R<bool, bool>;
207#[doc = "Write proxy for field `DMA2_CH2_IM`"]
208pub struct DMA2_CH2_IM_W<'a> {
209    w: &'a mut W,
210}
211impl<'a> DMA2_CH2_IM_W<'a> {
212    #[doc = r"Sets the field bit"]
213    #[inline(always)]
214    pub fn set_bit(self) -> &'a mut W {
215        self.bit(true)
216    }
217    #[doc = r"Clears the field bit"]
218    #[inline(always)]
219    pub fn clear_bit(self) -> &'a mut W {
220        self.bit(false)
221    }
222    #[doc = r"Writes raw bits to the field"]
223    #[inline(always)]
224    pub fn bit(self, value: bool) -> &'a mut W {
225        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
226        self.w
227    }
228}
229#[doc = "Reader of field `DMA2_CH3_IM`"]
230pub type DMA2_CH3_IM_R = crate::R<bool, bool>;
231#[doc = "Write proxy for field `DMA2_CH3_IM`"]
232pub struct DMA2_CH3_IM_W<'a> {
233    w: &'a mut W,
234}
235impl<'a> DMA2_CH3_IM_W<'a> {
236    #[doc = r"Sets the field bit"]
237    #[inline(always)]
238    pub fn set_bit(self) -> &'a mut W {
239        self.bit(true)
240    }
241    #[doc = r"Clears the field bit"]
242    #[inline(always)]
243    pub fn clear_bit(self) -> &'a mut W {
244        self.bit(false)
245    }
246    #[doc = r"Writes raw bits to the field"]
247    #[inline(always)]
248    pub fn bit(self, value: bool) -> &'a mut W {
249        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
250        self.w
251    }
252}
253#[doc = "Reader of field `DMA2_CH4_IM`"]
254pub type DMA2_CH4_IM_R = crate::R<bool, bool>;
255#[doc = "Write proxy for field `DMA2_CH4_IM`"]
256pub struct DMA2_CH4_IM_W<'a> {
257    w: &'a mut W,
258}
259impl<'a> DMA2_CH4_IM_W<'a> {
260    #[doc = r"Sets the field bit"]
261    #[inline(always)]
262    pub fn set_bit(self) -> &'a mut W {
263        self.bit(true)
264    }
265    #[doc = r"Clears the field bit"]
266    #[inline(always)]
267    pub fn clear_bit(self) -> &'a mut W {
268        self.bit(false)
269    }
270    #[doc = r"Writes raw bits to the field"]
271    #[inline(always)]
272    pub fn bit(self, value: bool) -> &'a mut W {
273        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
274        self.w
275    }
276}
277#[doc = "Reader of field `DMA2_CH5_IM`"]
278pub type DMA2_CH5_IM_R = crate::R<bool, bool>;
279#[doc = "Write proxy for field `DMA2_CH5_IM`"]
280pub struct DMA2_CH5_IM_W<'a> {
281    w: &'a mut W,
282}
283impl<'a> DMA2_CH5_IM_W<'a> {
284    #[doc = r"Sets the field bit"]
285    #[inline(always)]
286    pub fn set_bit(self) -> &'a mut W {
287        self.bit(true)
288    }
289    #[doc = r"Clears the field bit"]
290    #[inline(always)]
291    pub fn clear_bit(self) -> &'a mut W {
292        self.bit(false)
293    }
294    #[doc = r"Writes raw bits to the field"]
295    #[inline(always)]
296    pub fn bit(self, value: bool) -> &'a mut W {
297        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
298        self.w
299    }
300}
301#[doc = "Reader of field `DMA2_CH6_IM`"]
302pub type DMA2_CH6_IM_R = crate::R<bool, bool>;
303#[doc = "Write proxy for field `DMA2_CH6_IM`"]
304pub struct DMA2_CH6_IM_W<'a> {
305    w: &'a mut W,
306}
307impl<'a> DMA2_CH6_IM_W<'a> {
308    #[doc = r"Sets the field bit"]
309    #[inline(always)]
310    pub fn set_bit(self) -> &'a mut W {
311        self.bit(true)
312    }
313    #[doc = r"Clears the field bit"]
314    #[inline(always)]
315    pub fn clear_bit(self) -> &'a mut W {
316        self.bit(false)
317    }
318    #[doc = r"Writes raw bits to the field"]
319    #[inline(always)]
320    pub fn bit(self, value: bool) -> &'a mut W {
321        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
322        self.w
323    }
324}
325#[doc = "Reader of field `DMA2_CH7_IM`"]
326pub type DMA2_CH7_IM_R = crate::R<bool, bool>;
327#[doc = "Write proxy for field `DMA2_CH7_IM`"]
328pub struct DMA2_CH7_IM_W<'a> {
329    w: &'a mut W,
330}
331impl<'a> DMA2_CH7_IM_W<'a> {
332    #[doc = r"Sets the field bit"]
333    #[inline(always)]
334    pub fn set_bit(self) -> &'a mut W {
335        self.bit(true)
336    }
337    #[doc = r"Clears the field bit"]
338    #[inline(always)]
339    pub fn clear_bit(self) -> &'a mut W {
340        self.bit(false)
341    }
342    #[doc = r"Writes raw bits to the field"]
343    #[inline(always)]
344    pub fn bit(self, value: bool) -> &'a mut W {
345        self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
346        self.w
347    }
348}
349#[doc = "Reader of field `DMAM_UX1_IM`"]
350pub type DMAM_UX1_IM_R = crate::R<bool, bool>;
351#[doc = "Write proxy for field `DMAM_UX1_IM`"]
352pub struct DMAM_UX1_IM_W<'a> {
353    w: &'a mut W,
354}
355impl<'a> DMAM_UX1_IM_W<'a> {
356    #[doc = r"Sets the field bit"]
357    #[inline(always)]
358    pub fn set_bit(self) -> &'a mut W {
359        self.bit(true)
360    }
361    #[doc = r"Clears the field bit"]
362    #[inline(always)]
363    pub fn clear_bit(self) -> &'a mut W {
364        self.bit(false)
365    }
366    #[doc = r"Writes raw bits to the field"]
367    #[inline(always)]
368    pub fn bit(self, value: bool) -> &'a mut W {
369        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
370        self.w
371    }
372}
373#[doc = "Reader of field `PVM1IM`"]
374pub type PVM1IM_R = crate::R<bool, bool>;
375#[doc = "Write proxy for field `PVM1IM`"]
376pub struct PVM1IM_W<'a> {
377    w: &'a mut W,
378}
379impl<'a> PVM1IM_W<'a> {
380    #[doc = r"Sets the field bit"]
381    #[inline(always)]
382    pub fn set_bit(self) -> &'a mut W {
383        self.bit(true)
384    }
385    #[doc = r"Clears the field bit"]
386    #[inline(always)]
387    pub fn clear_bit(self) -> &'a mut W {
388        self.bit(false)
389    }
390    #[doc = r"Writes raw bits to the field"]
391    #[inline(always)]
392    pub fn bit(self, value: bool) -> &'a mut W {
393        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
394        self.w
395    }
396}
397#[doc = "Reader of field `PVM3IM`"]
398pub type PVM3IM_R = crate::R<bool, bool>;
399#[doc = "Write proxy for field `PVM3IM`"]
400pub struct PVM3IM_W<'a> {
401    w: &'a mut W,
402}
403impl<'a> PVM3IM_W<'a> {
404    #[doc = r"Sets the field bit"]
405    #[inline(always)]
406    pub fn set_bit(self) -> &'a mut W {
407        self.bit(true)
408    }
409    #[doc = r"Clears the field bit"]
410    #[inline(always)]
411    pub fn clear_bit(self) -> &'a mut W {
412        self.bit(false)
413    }
414    #[doc = r"Writes raw bits to the field"]
415    #[inline(always)]
416    pub fn bit(self, value: bool) -> &'a mut W {
417        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
418        self.w
419    }
420}
421#[doc = "Reader of field `PVDIM`"]
422pub type PVDIM_R = crate::R<bool, bool>;
423#[doc = "Write proxy for field `PVDIM`"]
424pub struct PVDIM_W<'a> {
425    w: &'a mut W,
426}
427impl<'a> PVDIM_W<'a> {
428    #[doc = r"Sets the field bit"]
429    #[inline(always)]
430    pub fn set_bit(self) -> &'a mut W {
431        self.bit(true)
432    }
433    #[doc = r"Clears the field bit"]
434    #[inline(always)]
435    pub fn clear_bit(self) -> &'a mut W {
436        self.bit(false)
437    }
438    #[doc = r"Writes raw bits to the field"]
439    #[inline(always)]
440    pub fn bit(self, value: bool) -> &'a mut W {
441        self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
442        self.w
443    }
444}
445#[doc = "Reader of field `TSCIM`"]
446pub type TSCIM_R = crate::R<bool, bool>;
447#[doc = "Write proxy for field `TSCIM`"]
448pub struct TSCIM_W<'a> {
449    w: &'a mut W,
450}
451impl<'a> TSCIM_W<'a> {
452    #[doc = r"Sets the field bit"]
453    #[inline(always)]
454    pub fn set_bit(self) -> &'a mut W {
455        self.bit(true)
456    }
457    #[doc = r"Clears the field bit"]
458    #[inline(always)]
459    pub fn clear_bit(self) -> &'a mut W {
460        self.bit(false)
461    }
462    #[doc = r"Writes raw bits to the field"]
463    #[inline(always)]
464    pub fn bit(self, value: bool) -> &'a mut W {
465        self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
466        self.w
467    }
468}
469#[doc = "Reader of field `LCDIM`"]
470pub type LCDIM_R = crate::R<bool, bool>;
471#[doc = "Write proxy for field `LCDIM`"]
472pub struct LCDIM_W<'a> {
473    w: &'a mut W,
474}
475impl<'a> LCDIM_W<'a> {
476    #[doc = r"Sets the field bit"]
477    #[inline(always)]
478    pub fn set_bit(self) -> &'a mut W {
479        self.bit(true)
480    }
481    #[doc = r"Clears the field bit"]
482    #[inline(always)]
483    pub fn clear_bit(self) -> &'a mut W {
484        self.bit(false)
485    }
486    #[doc = r"Writes raw bits to the field"]
487    #[inline(always)]
488    pub fn bit(self, value: bool) -> &'a mut W {
489        self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
490        self.w
491    }
492}
493impl R {
494    #[doc = "Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2"]
495    #[inline(always)]
496    pub fn dma1_ch1_im(&self) -> DMA1_CH1_IM_R {
497        DMA1_CH1_IM_R::new((self.bits & 0x01) != 0)
498    }
499    #[doc = "Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2"]
500    #[inline(always)]
501    pub fn dma1_ch2_im(&self) -> DMA1_CH2_IM_R {
502        DMA1_CH2_IM_R::new(((self.bits >> 1) & 0x01) != 0)
503    }
504    #[doc = "Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2"]
505    #[inline(always)]
506    pub fn dma1_ch3_im(&self) -> DMA1_CH3_IM_R {
507        DMA1_CH3_IM_R::new(((self.bits >> 2) & 0x01) != 0)
508    }
509    #[doc = "Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2"]
510    #[inline(always)]
511    pub fn dma1_ch4_im(&self) -> DMA1_CH4_IM_R {
512        DMA1_CH4_IM_R::new(((self.bits >> 3) & 0x01) != 0)
513    }
514    #[doc = "Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2"]
515    #[inline(always)]
516    pub fn dma1_ch5_im(&self) -> DMA1_CH5_IM_R {
517        DMA1_CH5_IM_R::new(((self.bits >> 4) & 0x01) != 0)
518    }
519    #[doc = "Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2"]
520    #[inline(always)]
521    pub fn dma1_ch6_im(&self) -> DMA1_CH6_IM_R {
522        DMA1_CH6_IM_R::new(((self.bits >> 5) & 0x01) != 0)
523    }
524    #[doc = "Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2"]
525    #[inline(always)]
526    pub fn dma1_ch7_im(&self) -> DMA1_CH7_IM_R {
527        DMA1_CH7_IM_R::new(((self.bits >> 6) & 0x01) != 0)
528    }
529    #[doc = "Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1"]
530    #[inline(always)]
531    pub fn dma2_ch1_im(&self) -> DMA2_CH1_IM_R {
532        DMA2_CH1_IM_R::new(((self.bits >> 8) & 0x01) != 0)
533    }
534    #[doc = "Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1"]
535    #[inline(always)]
536    pub fn dma2_ch2_im(&self) -> DMA2_CH2_IM_R {
537        DMA2_CH2_IM_R::new(((self.bits >> 9) & 0x01) != 0)
538    }
539    #[doc = "Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1"]
540    #[inline(always)]
541    pub fn dma2_ch3_im(&self) -> DMA2_CH3_IM_R {
542        DMA2_CH3_IM_R::new(((self.bits >> 10) & 0x01) != 0)
543    }
544    #[doc = "Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1"]
545    #[inline(always)]
546    pub fn dma2_ch4_im(&self) -> DMA2_CH4_IM_R {
547        DMA2_CH4_IM_R::new(((self.bits >> 11) & 0x01) != 0)
548    }
549    #[doc = "Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1"]
550    #[inline(always)]
551    pub fn dma2_ch5_im(&self) -> DMA2_CH5_IM_R {
552        DMA2_CH5_IM_R::new(((self.bits >> 12) & 0x01) != 0)
553    }
554    #[doc = "Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1"]
555    #[inline(always)]
556    pub fn dma2_ch6_im(&self) -> DMA2_CH6_IM_R {
557        DMA2_CH6_IM_R::new(((self.bits >> 13) & 0x01) != 0)
558    }
559    #[doc = "Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1"]
560    #[inline(always)]
561    pub fn dma2_ch7_im(&self) -> DMA2_CH7_IM_R {
562        DMA2_CH7_IM_R::new(((self.bits >> 14) & 0x01) != 0)
563    }
564    #[doc = "Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1"]
565    #[inline(always)]
566    pub fn dmam_ux1_im(&self) -> DMAM_UX1_IM_R {
567        DMAM_UX1_IM_R::new(((self.bits >> 15) & 0x01) != 0)
568    }
569    #[doc = "Bit 16 - Peripheral PVM1IM interrupt mask to CPU1"]
570    #[inline(always)]
571    pub fn pvm1im(&self) -> PVM1IM_R {
572        PVM1IM_R::new(((self.bits >> 16) & 0x01) != 0)
573    }
574    #[doc = "Bit 18 - Peripheral PVM3IM interrupt mask to CPU1"]
575    #[inline(always)]
576    pub fn pvm3im(&self) -> PVM3IM_R {
577        PVM3IM_R::new(((self.bits >> 18) & 0x01) != 0)
578    }
579    #[doc = "Bit 20 - Peripheral PVDIM interrupt mask to CPU1"]
580    #[inline(always)]
581    pub fn pvdim(&self) -> PVDIM_R {
582        PVDIM_R::new(((self.bits >> 20) & 0x01) != 0)
583    }
584    #[doc = "Bit 21 - Peripheral TSCIM interrupt mask to CPU1"]
585    #[inline(always)]
586    pub fn tscim(&self) -> TSCIM_R {
587        TSCIM_R::new(((self.bits >> 21) & 0x01) != 0)
588    }
589    #[doc = "Bit 22 - Peripheral LCDIM interrupt mask to CPU1"]
590    #[inline(always)]
591    pub fn lcdim(&self) -> LCDIM_R {
592        LCDIM_R::new(((self.bits >> 22) & 0x01) != 0)
593    }
594}
595impl W {
596    #[doc = "Bit 0 - Peripheral DMA1 CH1 interrupt mask to CPU2"]
597    #[inline(always)]
598    pub fn dma1_ch1_im(&mut self) -> DMA1_CH1_IM_W {
599        DMA1_CH1_IM_W { w: self }
600    }
601    #[doc = "Bit 1 - Peripheral DMA1 CH2 interrupt mask to CPU2"]
602    #[inline(always)]
603    pub fn dma1_ch2_im(&mut self) -> DMA1_CH2_IM_W {
604        DMA1_CH2_IM_W { w: self }
605    }
606    #[doc = "Bit 2 - Peripheral DMA1 CH3 interrupt mask to CPU2"]
607    #[inline(always)]
608    pub fn dma1_ch3_im(&mut self) -> DMA1_CH3_IM_W {
609        DMA1_CH3_IM_W { w: self }
610    }
611    #[doc = "Bit 3 - Peripheral DMA1 CH4 interrupt mask to CPU2"]
612    #[inline(always)]
613    pub fn dma1_ch4_im(&mut self) -> DMA1_CH4_IM_W {
614        DMA1_CH4_IM_W { w: self }
615    }
616    #[doc = "Bit 4 - Peripheral DMA1 CH5 interrupt mask to CPU2"]
617    #[inline(always)]
618    pub fn dma1_ch5_im(&mut self) -> DMA1_CH5_IM_W {
619        DMA1_CH5_IM_W { w: self }
620    }
621    #[doc = "Bit 5 - Peripheral DMA1 CH6 interrupt mask to CPU2"]
622    #[inline(always)]
623    pub fn dma1_ch6_im(&mut self) -> DMA1_CH6_IM_W {
624        DMA1_CH6_IM_W { w: self }
625    }
626    #[doc = "Bit 6 - Peripheral DMA1 CH7 interrupt mask to CPU2"]
627    #[inline(always)]
628    pub fn dma1_ch7_im(&mut self) -> DMA1_CH7_IM_W {
629        DMA1_CH7_IM_W { w: self }
630    }
631    #[doc = "Bit 8 - Peripheral DMA2 CH1 interrupt mask to CPU1"]
632    #[inline(always)]
633    pub fn dma2_ch1_im(&mut self) -> DMA2_CH1_IM_W {
634        DMA2_CH1_IM_W { w: self }
635    }
636    #[doc = "Bit 9 - Peripheral DMA2 CH2 interrupt mask to CPU1"]
637    #[inline(always)]
638    pub fn dma2_ch2_im(&mut self) -> DMA2_CH2_IM_W {
639        DMA2_CH2_IM_W { w: self }
640    }
641    #[doc = "Bit 10 - Peripheral DMA2 CH3 interrupt mask to CPU1"]
642    #[inline(always)]
643    pub fn dma2_ch3_im(&mut self) -> DMA2_CH3_IM_W {
644        DMA2_CH3_IM_W { w: self }
645    }
646    #[doc = "Bit 11 - Peripheral DMA2 CH4 interrupt mask to CPU1"]
647    #[inline(always)]
648    pub fn dma2_ch4_im(&mut self) -> DMA2_CH4_IM_W {
649        DMA2_CH4_IM_W { w: self }
650    }
651    #[doc = "Bit 12 - Peripheral DMA2 CH5 interrupt mask to CPU1"]
652    #[inline(always)]
653    pub fn dma2_ch5_im(&mut self) -> DMA2_CH5_IM_W {
654        DMA2_CH5_IM_W { w: self }
655    }
656    #[doc = "Bit 13 - Peripheral DMA2 CH6 interrupt mask to CPU1"]
657    #[inline(always)]
658    pub fn dma2_ch6_im(&mut self) -> DMA2_CH6_IM_W {
659        DMA2_CH6_IM_W { w: self }
660    }
661    #[doc = "Bit 14 - Peripheral DMA2 CH7 interrupt mask to CPU1"]
662    #[inline(always)]
663    pub fn dma2_ch7_im(&mut self) -> DMA2_CH7_IM_W {
664        DMA2_CH7_IM_W { w: self }
665    }
666    #[doc = "Bit 15 - Peripheral DMAM UX1 interrupt mask to CPU1"]
667    #[inline(always)]
668    pub fn dmam_ux1_im(&mut self) -> DMAM_UX1_IM_W {
669        DMAM_UX1_IM_W { w: self }
670    }
671    #[doc = "Bit 16 - Peripheral PVM1IM interrupt mask to CPU1"]
672    #[inline(always)]
673    pub fn pvm1im(&mut self) -> PVM1IM_W {
674        PVM1IM_W { w: self }
675    }
676    #[doc = "Bit 18 - Peripheral PVM3IM interrupt mask to CPU1"]
677    #[inline(always)]
678    pub fn pvm3im(&mut self) -> PVM3IM_W {
679        PVM3IM_W { w: self }
680    }
681    #[doc = "Bit 20 - Peripheral PVDIM interrupt mask to CPU1"]
682    #[inline(always)]
683    pub fn pvdim(&mut self) -> PVDIM_W {
684        PVDIM_W { w: self }
685    }
686    #[doc = "Bit 21 - Peripheral TSCIM interrupt mask to CPU1"]
687    #[inline(always)]
688    pub fn tscim(&mut self) -> TSCIM_W {
689        TSCIM_W { w: self }
690    }
691    #[doc = "Bit 22 - Peripheral LCDIM interrupt mask to CPU1"]
692    #[inline(always)]
693    pub fn lcdim(&mut self) -> LCDIM_W {
694        LCDIM_W { w: self }
695    }
696}
stm32wb_pac/syscfg/c2imr2.rs

stm32wb_pac/syscfg/
c2imr2.rs
