stm32wb_pac/spi1/
sr.rs

1#[doc = "Reader of register SR"]
2pub type R = crate::R<u32, super::SR>;
3#[doc = "Writer for register SR"]
4pub type W = crate::W<u32, super::SR>;
5#[doc = "Register SR `reset()`'s with value 0x02"]
6impl crate::ResetValue for super::SR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x02
11    }
12}
13#[doc = "Reader of field `RXNE`"]
14pub type RXNE_R = crate::R<bool, bool>;
15#[doc = "Reader of field `TXE`"]
16pub type TXE_R = crate::R<bool, bool>;
17#[doc = "Reader of field `CRCERR`"]
18pub type CRCERR_R = crate::R<bool, bool>;
19#[doc = "Write proxy for field `CRCERR`"]
20pub struct CRCERR_W<'a> {
21    w: &'a mut W,
22}
23impl<'a> CRCERR_W<'a> {
24    #[doc = r"Sets the field bit"]
25    #[inline(always)]
26    pub fn set_bit(self) -> &'a mut W {
27        self.bit(true)
28    }
29    #[doc = r"Clears the field bit"]
30    #[inline(always)]
31    pub fn clear_bit(self) -> &'a mut W {
32        self.bit(false)
33    }
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub fn bit(self, value: bool) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
38        self.w
39    }
40}
41#[doc = "Reader of field `MODF`"]
42pub type MODF_R = crate::R<bool, bool>;
43#[doc = "Reader of field `OVR`"]
44pub type OVR_R = crate::R<bool, bool>;
45#[doc = "Reader of field `BSY`"]
46pub type BSY_R = crate::R<bool, bool>;
47#[doc = "Reader of field `TIFRFE`"]
48pub type TIFRFE_R = crate::R<bool, bool>;
49#[doc = "Reader of field `FRLVL`"]
50pub type FRLVL_R = crate::R<u8, u8>;
51#[doc = "Reader of field `FTLVL`"]
52pub type FTLVL_R = crate::R<u8, u8>;
53impl R {
54    #[doc = "Bit 0 - Receive buffer not empty"]
55    #[inline(always)]
56    pub fn rxne(&self) -> RXNE_R {
57        RXNE_R::new((self.bits & 0x01) != 0)
58    }
59    #[doc = "Bit 1 - Transmit buffer empty"]
60    #[inline(always)]
61    pub fn txe(&self) -> TXE_R {
62        TXE_R::new(((self.bits >> 1) & 0x01) != 0)
63    }
64    #[doc = "Bit 4 - CRC error flag"]
65    #[inline(always)]
66    pub fn crcerr(&self) -> CRCERR_R {
67        CRCERR_R::new(((self.bits >> 4) & 0x01) != 0)
68    }
69    #[doc = "Bit 5 - Mode fault"]
70    #[inline(always)]
71    pub fn modf(&self) -> MODF_R {
72        MODF_R::new(((self.bits >> 5) & 0x01) != 0)
73    }
74    #[doc = "Bit 6 - Overrun flag"]
75    #[inline(always)]
76    pub fn ovr(&self) -> OVR_R {
77        OVR_R::new(((self.bits >> 6) & 0x01) != 0)
78    }
79    #[doc = "Bit 7 - Busy flag"]
80    #[inline(always)]
81    pub fn bsy(&self) -> BSY_R {
82        BSY_R::new(((self.bits >> 7) & 0x01) != 0)
83    }
84    #[doc = "Bit 8 - TI frame format error"]
85    #[inline(always)]
86    pub fn tifrfe(&self) -> TIFRFE_R {
87        TIFRFE_R::new(((self.bits >> 8) & 0x01) != 0)
88    }
89    #[doc = "Bits 9:10 - FIFO reception level"]
90    #[inline(always)]
91    pub fn frlvl(&self) -> FRLVL_R {
92        FRLVL_R::new(((self.bits >> 9) & 0x03) as u8)
93    }
94    #[doc = "Bits 11:12 - FIFO transmission level"]
95    #[inline(always)]
96    pub fn ftlvl(&self) -> FTLVL_R {
97        FTLVL_R::new(((self.bits >> 11) & 0x03) as u8)
98    }
99}
100impl W {
101    #[doc = "Bit 4 - CRC error flag"]
102    #[inline(always)]
103    pub fn crcerr(&mut self) -> CRCERR_W {
104        CRCERR_W { w: self }
105    }
106}
stm32wb_pac/spi1/sr.rs

stm32wb_pac/spi1/
sr.rs
