1#[doc = "Reader of register CR2"]
2pub type R = crate::R<u32, super::CR2>;
3#[doc = "Writer for register CR2"]
4pub type W = crate::W<u32, super::CR2>;
5#[doc = "Register CR2 `reset()`'s with value 0x0700"]
6impl crate::ResetValue for super::CR2 {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x0700
11 }
12}
13#[doc = "Reader of field `RXDMAEN`"]
14pub type RXDMAEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `RXDMAEN`"]
16pub struct RXDMAEN_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> RXDMAEN_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `TXDMAEN`"]
38pub type TXDMAEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `TXDMAEN`"]
40pub struct TXDMAEN_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> TXDMAEN_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `SSOE`"]
62pub type SSOE_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `SSOE`"]
64pub struct SSOE_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> SSOE_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
82 self.w
83 }
84}
85#[doc = "Reader of field `NSSP`"]
86pub type NSSP_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `NSSP`"]
88pub struct NSSP_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> NSSP_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
106 self.w
107 }
108}
109#[doc = "Reader of field `FRF`"]
110pub type FRF_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `FRF`"]
112pub struct FRF_W<'a> {
113 w: &'a mut W,
114}
115impl<'a> FRF_W<'a> {
116 #[doc = r"Sets the field bit"]
117 #[inline(always)]
118 pub fn set_bit(self) -> &'a mut W {
119 self.bit(true)
120 }
121 #[doc = r"Clears the field bit"]
122 #[inline(always)]
123 pub fn clear_bit(self) -> &'a mut W {
124 self.bit(false)
125 }
126 #[doc = r"Writes raw bits to the field"]
127 #[inline(always)]
128 pub fn bit(self, value: bool) -> &'a mut W {
129 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
130 self.w
131 }
132}
133#[doc = "Reader of field `ERRIE`"]
134pub type ERRIE_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `ERRIE`"]
136pub struct ERRIE_W<'a> {
137 w: &'a mut W,
138}
139impl<'a> ERRIE_W<'a> {
140 #[doc = r"Sets the field bit"]
141 #[inline(always)]
142 pub fn set_bit(self) -> &'a mut W {
143 self.bit(true)
144 }
145 #[doc = r"Clears the field bit"]
146 #[inline(always)]
147 pub fn clear_bit(self) -> &'a mut W {
148 self.bit(false)
149 }
150 #[doc = r"Writes raw bits to the field"]
151 #[inline(always)]
152 pub fn bit(self, value: bool) -> &'a mut W {
153 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
154 self.w
155 }
156}
157#[doc = "Reader of field `RXNEIE`"]
158pub type RXNEIE_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `RXNEIE`"]
160pub struct RXNEIE_W<'a> {
161 w: &'a mut W,
162}
163impl<'a> RXNEIE_W<'a> {
164 #[doc = r"Sets the field bit"]
165 #[inline(always)]
166 pub fn set_bit(self) -> &'a mut W {
167 self.bit(true)
168 }
169 #[doc = r"Clears the field bit"]
170 #[inline(always)]
171 pub fn clear_bit(self) -> &'a mut W {
172 self.bit(false)
173 }
174 #[doc = r"Writes raw bits to the field"]
175 #[inline(always)]
176 pub fn bit(self, value: bool) -> &'a mut W {
177 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
178 self.w
179 }
180}
181#[doc = "Reader of field `TXEIE`"]
182pub type TXEIE_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `TXEIE`"]
184pub struct TXEIE_W<'a> {
185 w: &'a mut W,
186}
187impl<'a> TXEIE_W<'a> {
188 #[doc = r"Sets the field bit"]
189 #[inline(always)]
190 pub fn set_bit(self) -> &'a mut W {
191 self.bit(true)
192 }
193 #[doc = r"Clears the field bit"]
194 #[inline(always)]
195 pub fn clear_bit(self) -> &'a mut W {
196 self.bit(false)
197 }
198 #[doc = r"Writes raw bits to the field"]
199 #[inline(always)]
200 pub fn bit(self, value: bool) -> &'a mut W {
201 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
202 self.w
203 }
204}
205#[doc = "Reader of field `DS`"]
206pub type DS_R = crate::R<u8, u8>;
207#[doc = "Write proxy for field `DS`"]
208pub struct DS_W<'a> {
209 w: &'a mut W,
210}
211impl<'a> DS_W<'a> {
212 #[doc = r"Writes raw bits to the field"]
213 #[inline(always)]
214 pub unsafe fn bits(self, value: u8) -> &'a mut W {
215 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
216 self.w
217 }
218}
219#[doc = "Reader of field `FRXTH`"]
220pub type FRXTH_R = crate::R<bool, bool>;
221#[doc = "Write proxy for field `FRXTH`"]
222pub struct FRXTH_W<'a> {
223 w: &'a mut W,
224}
225impl<'a> FRXTH_W<'a> {
226 #[doc = r"Sets the field bit"]
227 #[inline(always)]
228 pub fn set_bit(self) -> &'a mut W {
229 self.bit(true)
230 }
231 #[doc = r"Clears the field bit"]
232 #[inline(always)]
233 pub fn clear_bit(self) -> &'a mut W {
234 self.bit(false)
235 }
236 #[doc = r"Writes raw bits to the field"]
237 #[inline(always)]
238 pub fn bit(self, value: bool) -> &'a mut W {
239 self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
240 self.w
241 }
242}
243#[doc = "Reader of field `LDMA_RX`"]
244pub type LDMA_RX_R = crate::R<bool, bool>;
245#[doc = "Write proxy for field `LDMA_RX`"]
246pub struct LDMA_RX_W<'a> {
247 w: &'a mut W,
248}
249impl<'a> LDMA_RX_W<'a> {
250 #[doc = r"Sets the field bit"]
251 #[inline(always)]
252 pub fn set_bit(self) -> &'a mut W {
253 self.bit(true)
254 }
255 #[doc = r"Clears the field bit"]
256 #[inline(always)]
257 pub fn clear_bit(self) -> &'a mut W {
258 self.bit(false)
259 }
260 #[doc = r"Writes raw bits to the field"]
261 #[inline(always)]
262 pub fn bit(self, value: bool) -> &'a mut W {
263 self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
264 self.w
265 }
266}
267#[doc = "Reader of field `LDMA_TX`"]
268pub type LDMA_TX_R = crate::R<bool, bool>;
269#[doc = "Write proxy for field `LDMA_TX`"]
270pub struct LDMA_TX_W<'a> {
271 w: &'a mut W,
272}
273impl<'a> LDMA_TX_W<'a> {
274 #[doc = r"Sets the field bit"]
275 #[inline(always)]
276 pub fn set_bit(self) -> &'a mut W {
277 self.bit(true)
278 }
279 #[doc = r"Clears the field bit"]
280 #[inline(always)]
281 pub fn clear_bit(self) -> &'a mut W {
282 self.bit(false)
283 }
284 #[doc = r"Writes raw bits to the field"]
285 #[inline(always)]
286 pub fn bit(self, value: bool) -> &'a mut W {
287 self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
288 self.w
289 }
290}
291impl R {
292 #[doc = "Bit 0 - Rx buffer DMA enable"]
293 #[inline(always)]
294 pub fn rxdmaen(&self) -> RXDMAEN_R {
295 RXDMAEN_R::new((self.bits & 0x01) != 0)
296 }
297 #[doc = "Bit 1 - Tx buffer DMA enable"]
298 #[inline(always)]
299 pub fn txdmaen(&self) -> TXDMAEN_R {
300 TXDMAEN_R::new(((self.bits >> 1) & 0x01) != 0)
301 }
302 #[doc = "Bit 2 - SS output enable"]
303 #[inline(always)]
304 pub fn ssoe(&self) -> SSOE_R {
305 SSOE_R::new(((self.bits >> 2) & 0x01) != 0)
306 }
307 #[doc = "Bit 3 - NSS pulse management"]
308 #[inline(always)]
309 pub fn nssp(&self) -> NSSP_R {
310 NSSP_R::new(((self.bits >> 3) & 0x01) != 0)
311 }
312 #[doc = "Bit 4 - Frame format"]
313 #[inline(always)]
314 pub fn frf(&self) -> FRF_R {
315 FRF_R::new(((self.bits >> 4) & 0x01) != 0)
316 }
317 #[doc = "Bit 5 - Error interrupt enable"]
318 #[inline(always)]
319 pub fn errie(&self) -> ERRIE_R {
320 ERRIE_R::new(((self.bits >> 5) & 0x01) != 0)
321 }
322 #[doc = "Bit 6 - RX buffer not empty interrupt enable"]
323 #[inline(always)]
324 pub fn rxneie(&self) -> RXNEIE_R {
325 RXNEIE_R::new(((self.bits >> 6) & 0x01) != 0)
326 }
327 #[doc = "Bit 7 - Tx buffer empty interrupt enable"]
328 #[inline(always)]
329 pub fn txeie(&self) -> TXEIE_R {
330 TXEIE_R::new(((self.bits >> 7) & 0x01) != 0)
331 }
332 #[doc = "Bits 8:11 - Data size"]
333 #[inline(always)]
334 pub fn ds(&self) -> DS_R {
335 DS_R::new(((self.bits >> 8) & 0x0f) as u8)
336 }
337 #[doc = "Bit 12 - FIFO reception threshold"]
338 #[inline(always)]
339 pub fn frxth(&self) -> FRXTH_R {
340 FRXTH_R::new(((self.bits >> 12) & 0x01) != 0)
341 }
342 #[doc = "Bit 13 - Last DMA transfer for reception"]
343 #[inline(always)]
344 pub fn ldma_rx(&self) -> LDMA_RX_R {
345 LDMA_RX_R::new(((self.bits >> 13) & 0x01) != 0)
346 }
347 #[doc = "Bit 14 - Last DMA transfer for transmission"]
348 #[inline(always)]
349 pub fn ldma_tx(&self) -> LDMA_TX_R {
350 LDMA_TX_R::new(((self.bits >> 14) & 0x01) != 0)
351 }
352}
353impl W {
354 #[doc = "Bit 0 - Rx buffer DMA enable"]
355 #[inline(always)]
356 pub fn rxdmaen(&mut self) -> RXDMAEN_W {
357 RXDMAEN_W { w: self }
358 }
359 #[doc = "Bit 1 - Tx buffer DMA enable"]
360 #[inline(always)]
361 pub fn txdmaen(&mut self) -> TXDMAEN_W {
362 TXDMAEN_W { w: self }
363 }
364 #[doc = "Bit 2 - SS output enable"]
365 #[inline(always)]
366 pub fn ssoe(&mut self) -> SSOE_W {
367 SSOE_W { w: self }
368 }
369 #[doc = "Bit 3 - NSS pulse management"]
370 #[inline(always)]
371 pub fn nssp(&mut self) -> NSSP_W {
372 NSSP_W { w: self }
373 }
374 #[doc = "Bit 4 - Frame format"]
375 #[inline(always)]
376 pub fn frf(&mut self) -> FRF_W {
377 FRF_W { w: self }
378 }
379 #[doc = "Bit 5 - Error interrupt enable"]
380 #[inline(always)]
381 pub fn errie(&mut self) -> ERRIE_W {
382 ERRIE_W { w: self }
383 }
384 #[doc = "Bit 6 - RX buffer not empty interrupt enable"]
385 #[inline(always)]
386 pub fn rxneie(&mut self) -> RXNEIE_W {
387 RXNEIE_W { w: self }
388 }
389 #[doc = "Bit 7 - Tx buffer empty interrupt enable"]
390 #[inline(always)]
391 pub fn txeie(&mut self) -> TXEIE_W {
392 TXEIE_W { w: self }
393 }
394 #[doc = "Bits 8:11 - Data size"]
395 #[inline(always)]
396 pub fn ds(&mut self) -> DS_W {
397 DS_W { w: self }
398 }
399 #[doc = "Bit 12 - FIFO reception threshold"]
400 #[inline(always)]
401 pub fn frxth(&mut self) -> FRXTH_W {
402 FRXTH_W { w: self }
403 }
404 #[doc = "Bit 13 - Last DMA transfer for reception"]
405 #[inline(always)]
406 pub fn ldma_rx(&mut self) -> LDMA_RX_W {
407 LDMA_RX_W { w: self }
408 }
409 #[doc = "Bit 14 - Last DMA transfer for transmission"]
410 #[inline(always)]
411 pub fn ldma_tx(&mut self) -> LDMA_TX_W {
412 LDMA_TX_W { w: self }
413 }
414}