stm32wb_pac/rtc/
shiftr.rs

1#[doc = "Writer for register SHIFTR"]
2pub type W = crate::W<u32, super::SHIFTR>;
3#[doc = "Register SHIFTR `reset()`'s with value 0"]
4impl crate::ResetValue for super::SHIFTR {
5    type Type = u32;
6    #[inline(always)]
7    fn reset_value() -> Self::Type {
8        0
9    }
10}
11#[doc = "Write proxy for field `ADD1S`"]
12pub struct ADD1S_W<'a> {
13    w: &'a mut W,
14}
15impl<'a> ADD1S_W<'a> {
16    #[doc = r"Sets the field bit"]
17    #[inline(always)]
18    pub fn set_bit(self) -> &'a mut W {
19        self.bit(true)
20    }
21    #[doc = r"Clears the field bit"]
22    #[inline(always)]
23    pub fn clear_bit(self) -> &'a mut W {
24        self.bit(false)
25    }
26    #[doc = r"Writes raw bits to the field"]
27    #[inline(always)]
28    pub fn bit(self, value: bool) -> &'a mut W {
29        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
30        self.w
31    }
32}
33#[doc = "Write proxy for field `SUBFS`"]
34pub struct SUBFS_W<'a> {
35    w: &'a mut W,
36}
37impl<'a> SUBFS_W<'a> {
38    #[doc = r"Writes raw bits to the field"]
39    #[inline(always)]
40    pub unsafe fn bits(self, value: u16) -> &'a mut W {
41        self.w.bits = (self.w.bits & !0x7fff) | ((value as u32) & 0x7fff);
42        self.w
43    }
44}
45impl W {
46    #[doc = "Bit 31 - Add one second"]
47    #[inline(always)]
48    pub fn add1s(&mut self) -> ADD1S_W {
49        ADD1S_W { w: self }
50    }
51    #[doc = "Bits 0:14 - Subtract a fraction of a second"]
52    #[inline(always)]
53    pub fn subfs(&mut self) -> SUBFS_W {
54        SUBFS_W { w: self }
55    }
56}
stm32wb_pac/rtc/shiftr.rs

stm32wb_pac/rtc/
shiftr.rs
