stm32wb_pac/rcc/
pllsai1cfgr.rs

1#[doc = "Reader of register PLLSAI1CFGR"]
2pub type R = crate::R<u32, super::PLLSAI1CFGR>;
3#[doc = "Writer for register PLLSAI1CFGR"]
4pub type W = crate::W<u32, super::PLLSAI1CFGR>;
5#[doc = "Register PLLSAI1CFGR `reset()`'s with value 0x2204_0100"]
6impl crate::ResetValue for super::PLLSAI1CFGR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x2204_0100
11    }
12}
13#[doc = "Reader of field `PLLR`"]
14pub type PLLR_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `PLLR`"]
16pub struct PLLR_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> PLLR_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
24        self.w
25    }
26}
27#[doc = "Reader of field `PLLREN`"]
28pub type PLLREN_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `PLLREN`"]
30pub struct PLLREN_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> PLLREN_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
48        self.w
49    }
50}
51#[doc = "Reader of field `PLLQ`"]
52pub type PLLQ_R = crate::R<u8, u8>;
53#[doc = "Write proxy for field `PLLQ`"]
54pub struct PLLQ_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> PLLQ_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
62        self.w
63    }
64}
65#[doc = "Reader of field `PLLQEN`"]
66pub type PLLQEN_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `PLLQEN`"]
68pub struct PLLQEN_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> PLLQEN_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
86        self.w
87    }
88}
89#[doc = "Reader of field `PLLP`"]
90pub type PLLP_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `PLLP`"]
92pub struct PLLP_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> PLLP_W<'a> {
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub unsafe fn bits(self, value: u8) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
100        self.w
101    }
102}
103#[doc = "Reader of field `PLLPEN`"]
104pub type PLLPEN_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `PLLPEN`"]
106pub struct PLLPEN_W<'a> {
107    w: &'a mut W,
108}
109impl<'a> PLLPEN_W<'a> {
110    #[doc = r"Sets the field bit"]
111    #[inline(always)]
112    pub fn set_bit(self) -> &'a mut W {
113        self.bit(true)
114    }
115    #[doc = r"Clears the field bit"]
116    #[inline(always)]
117    pub fn clear_bit(self) -> &'a mut W {
118        self.bit(false)
119    }
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub fn bit(self, value: bool) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
124        self.w
125    }
126}
127#[doc = "Reader of field `PLLN`"]
128pub type PLLN_R = crate::R<u8, u8>;
129#[doc = "Write proxy for field `PLLN`"]
130pub struct PLLN_W<'a> {
131    w: &'a mut W,
132}
133impl<'a> PLLN_W<'a> {
134    #[doc = r"Writes raw bits to the field"]
135    #[inline(always)]
136    pub unsafe fn bits(self, value: u8) -> &'a mut W {
137        self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
138        self.w
139    }
140}
141impl R {
142    #[doc = "Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)"]
143    #[inline(always)]
144    pub fn pllr(&self) -> PLLR_R {
145        PLLR_R::new(((self.bits >> 29) & 0x07) as u8)
146    }
147    #[doc = "Bit 28 - PLLSAI PLLADC1CLK output enable"]
148    #[inline(always)]
149    pub fn pllren(&self) -> PLLREN_R {
150        PLLREN_R::new(((self.bits >> 28) & 0x01) != 0)
151    }
152    #[doc = "Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)"]
153    #[inline(always)]
154    pub fn pllq(&self) -> PLLQ_R {
155        PLLQ_R::new(((self.bits >> 25) & 0x07) as u8)
156    }
157    #[doc = "Bit 24 - SAIPLL PLLSAIUSBCLK output enable"]
158    #[inline(always)]
159    pub fn pllqen(&self) -> PLLQEN_R {
160        PLLQEN_R::new(((self.bits >> 24) & 0x01) != 0)
161    }
162    #[doc = "Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)"]
163    #[inline(always)]
164    pub fn pllp(&self) -> PLLP_R {
165        PLLP_R::new(((self.bits >> 17) & 0x1f) as u8)
166    }
167    #[doc = "Bit 16 - SAIPLL PLLSAI1CLK output enable"]
168    #[inline(always)]
169    pub fn pllpen(&self) -> PLLPEN_R {
170        PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0)
171    }
172    #[doc = "Bits 8:14 - SAIPLL multiplication factor for VCO"]
173    #[inline(always)]
174    pub fn plln(&self) -> PLLN_R {
175        PLLN_R::new(((self.bits >> 8) & 0x7f) as u8)
176    }
177}
178impl W {
179    #[doc = "Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)"]
180    #[inline(always)]
181    pub fn pllr(&mut self) -> PLLR_W {
182        PLLR_W { w: self }
183    }
184    #[doc = "Bit 28 - PLLSAI PLLADC1CLK output enable"]
185    #[inline(always)]
186    pub fn pllren(&mut self) -> PLLREN_W {
187        PLLREN_W { w: self }
188    }
189    #[doc = "Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)"]
190    #[inline(always)]
191    pub fn pllq(&mut self) -> PLLQ_W {
192        PLLQ_W { w: self }
193    }
194    #[doc = "Bit 24 - SAIPLL PLLSAIUSBCLK output enable"]
195    #[inline(always)]
196    pub fn pllqen(&mut self) -> PLLQEN_W {
197        PLLQEN_W { w: self }
198    }
199    #[doc = "Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)"]
200    #[inline(always)]
201    pub fn pllp(&mut self) -> PLLP_W {
202        PLLP_W { w: self }
203    }
204    #[doc = "Bit 16 - SAIPLL PLLSAI1CLK output enable"]
205    #[inline(always)]
206    pub fn pllpen(&mut self) -> PLLPEN_W {
207        PLLPEN_W { w: self }
208    }
209    #[doc = "Bits 8:14 - SAIPLL multiplication factor for VCO"]
210    #[inline(always)]
211    pub fn plln(&mut self) -> PLLN_W {
212        PLLN_W { w: self }
213    }
214}
stm32wb_pac/rcc/pllsai1cfgr.rs

stm32wb_pac/rcc/
pllsai1cfgr.rs
