stm32wb_pac/rcc/
icscr.rs

1#[doc = "Reader of register ICSCR"]
2pub type R = crate::R<u32, super::ICSCR>;
3#[doc = "Writer for register ICSCR"]
4pub type W = crate::W<u32, super::ICSCR>;
5#[doc = "Register ICSCR `reset()`'s with value 0x4000_0000"]
6impl crate::ResetValue for super::ICSCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x4000_0000
11    }
12}
13#[doc = "Reader of field `HSITRIM`"]
14pub type HSITRIM_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `HSITRIM`"]
16pub struct HSITRIM_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> HSITRIM_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x7f << 24)) | (((value as u32) & 0x7f) << 24);
24        self.w
25    }
26}
27#[doc = "Reader of field `HSICAL`"]
28pub type HSICAL_R = crate::R<u8, u8>;
29#[doc = "Reader of field `MSITRIM`"]
30pub type MSITRIM_R = crate::R<u8, u8>;
31#[doc = "Write proxy for field `MSITRIM`"]
32pub struct MSITRIM_W<'a> {
33    w: &'a mut W,
34}
35impl<'a> MSITRIM_W<'a> {
36    #[doc = r"Writes raw bits to the field"]
37    #[inline(always)]
38    pub unsafe fn bits(self, value: u8) -> &'a mut W {
39        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
40        self.w
41    }
42}
43#[doc = "Reader of field `MSICAL`"]
44pub type MSICAL_R = crate::R<u8, u8>;
45impl R {
46    #[doc = "Bits 24:30 - HSI clock trimming"]
47    #[inline(always)]
48    pub fn hsitrim(&self) -> HSITRIM_R {
49        HSITRIM_R::new(((self.bits >> 24) & 0x7f) as u8)
50    }
51    #[doc = "Bits 16:23 - HSI clock calibration"]
52    #[inline(always)]
53    pub fn hsical(&self) -> HSICAL_R {
54        HSICAL_R::new(((self.bits >> 16) & 0xff) as u8)
55    }
56    #[doc = "Bits 8:15 - MSI clock trimming"]
57    #[inline(always)]
58    pub fn msitrim(&self) -> MSITRIM_R {
59        MSITRIM_R::new(((self.bits >> 8) & 0xff) as u8)
60    }
61    #[doc = "Bits 0:7 - MSI clock calibration"]
62    #[inline(always)]
63    pub fn msical(&self) -> MSICAL_R {
64        MSICAL_R::new((self.bits & 0xff) as u8)
65    }
66}
67impl W {
68    #[doc = "Bits 24:30 - HSI clock trimming"]
69    #[inline(always)]
70    pub fn hsitrim(&mut self) -> HSITRIM_W {
71        HSITRIM_W { w: self }
72    }
73    #[doc = "Bits 8:15 - MSI clock trimming"]
74    #[inline(always)]
75    pub fn msitrim(&mut self) -> MSITRIM_W {
76        MSITRIM_W { w: self }
77    }
78}
stm32wb_pac/rcc/icscr.rs

stm32wb_pac/rcc/
icscr.rs
