stm32wb_pac/rcc/
crrcr.rs

1#[doc = "Reader of register CRRCR"]
2pub type R = crate::R<u32, super::CRRCR>;
3#[doc = "Writer for register CRRCR"]
4pub type W = crate::W<u32, super::CRRCR>;
5#[doc = "Register CRRCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CRRCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `HSI48CAL`"]
14pub type HSI48CAL_R = crate::R<u16, u16>;
15#[doc = "Reader of field `HSI48RDY`"]
16pub type HSI48RDY_R = crate::R<bool, bool>;
17#[doc = "Reader of field `HSI48ON`"]
18pub type HSI48ON_R = crate::R<bool, bool>;
19#[doc = "Write proxy for field `HSI48ON`"]
20pub struct HSI48ON_W<'a> {
21    w: &'a mut W,
22}
23impl<'a> HSI48ON_W<'a> {
24    #[doc = r"Sets the field bit"]
25    #[inline(always)]
26    pub fn set_bit(self) -> &'a mut W {
27        self.bit(true)
28    }
29    #[doc = r"Clears the field bit"]
30    #[inline(always)]
31    pub fn clear_bit(self) -> &'a mut W {
32        self.bit(false)
33    }
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub fn bit(self, value: bool) -> &'a mut W {
37        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
38        self.w
39    }
40}
41impl R {
42    #[doc = "Bits 7:15 - HSI48 clock calibration"]
43    #[inline(always)]
44    pub fn hsi48cal(&self) -> HSI48CAL_R {
45        HSI48CAL_R::new(((self.bits >> 7) & 0x01ff) as u16)
46    }
47    #[doc = "Bit 1 - HSI48 clock ready"]
48    #[inline(always)]
49    pub fn hsi48rdy(&self) -> HSI48RDY_R {
50        HSI48RDY_R::new(((self.bits >> 1) & 0x01) != 0)
51    }
52    #[doc = "Bit 0 - HSI48 oscillator enabled"]
53    #[inline(always)]
54    pub fn hsi48on(&self) -> HSI48ON_R {
55        HSI48ON_R::new((self.bits & 0x01) != 0)
56    }
57}
58impl W {
59    #[doc = "Bit 0 - HSI48 oscillator enabled"]
60    #[inline(always)]
61    pub fn hsi48on(&mut self) -> HSI48ON_W {
62        HSI48ON_W { w: self }
63    }
64}