1#[doc = "Reader of register CCIPR"]
2pub type R = crate::R<u32, super::CCIPR>;
3#[doc = "Writer for register CCIPR"]
4pub type W = crate::W<u32, super::CCIPR>;
5#[doc = "Register CCIPR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CCIPR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `RNGSEL`"]
14pub type RNGSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `RNGSEL`"]
16pub struct RNGSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> RNGSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x03 << 30)) | (((value as u32) & 0x03) << 30);
24 self.w
25 }
26}
27#[doc = "Reader of field `ADCSEL`"]
28pub type ADCSEL_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `ADCSEL`"]
30pub struct ADCSEL_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> ADCSEL_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
38 self.w
39 }
40}
41#[doc = "Reader of field `CLK48SEL`"]
42pub type CLK48SEL_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `CLK48SEL`"]
44pub struct CLK48SEL_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> CLK48SEL_W<'a> {
48 #[doc = r"Writes raw bits to the field"]
49 #[inline(always)]
50 pub unsafe fn bits(self, value: u8) -> &'a mut W {
51 self.w.bits = (self.w.bits & !(0x03 << 26)) | (((value as u32) & 0x03) << 26);
52 self.w
53 }
54}
55#[doc = "Reader of field `SAI1SEL`"]
56pub type SAI1SEL_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `SAI1SEL`"]
58pub struct SAI1SEL_W<'a> {
59 w: &'a mut W,
60}
61impl<'a> SAI1SEL_W<'a> {
62 #[doc = r"Writes raw bits to the field"]
63 #[inline(always)]
64 pub unsafe fn bits(self, value: u8) -> &'a mut W {
65 self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
66 self.w
67 }
68}
69#[doc = "Reader of field `LPTIM2SEL`"]
70pub type LPTIM2SEL_R = crate::R<u8, u8>;
71#[doc = "Write proxy for field `LPTIM2SEL`"]
72pub struct LPTIM2SEL_W<'a> {
73 w: &'a mut W,
74}
75impl<'a> LPTIM2SEL_W<'a> {
76 #[doc = r"Writes raw bits to the field"]
77 #[inline(always)]
78 pub unsafe fn bits(self, value: u8) -> &'a mut W {
79 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
80 self.w
81 }
82}
83#[doc = "Reader of field `LPTIM1SEL`"]
84pub type LPTIM1SEL_R = crate::R<u8, u8>;
85#[doc = "Write proxy for field `LPTIM1SEL`"]
86pub struct LPTIM1SEL_W<'a> {
87 w: &'a mut W,
88}
89impl<'a> LPTIM1SEL_W<'a> {
90 #[doc = r"Writes raw bits to the field"]
91 #[inline(always)]
92 pub unsafe fn bits(self, value: u8) -> &'a mut W {
93 self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
94 self.w
95 }
96}
97#[doc = "Reader of field `I2C3SEL`"]
98pub type I2C3SEL_R = crate::R<u8, u8>;
99#[doc = "Write proxy for field `I2C3SEL`"]
100pub struct I2C3SEL_W<'a> {
101 w: &'a mut W,
102}
103impl<'a> I2C3SEL_W<'a> {
104 #[doc = r"Writes raw bits to the field"]
105 #[inline(always)]
106 pub unsafe fn bits(self, value: u8) -> &'a mut W {
107 self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
108 self.w
109 }
110}
111#[doc = "Reader of field `I2C1SEL`"]
112pub type I2C1SEL_R = crate::R<u8, u8>;
113#[doc = "Write proxy for field `I2C1SEL`"]
114pub struct I2C1SEL_W<'a> {
115 w: &'a mut W,
116}
117impl<'a> I2C1SEL_W<'a> {
118 #[doc = r"Writes raw bits to the field"]
119 #[inline(always)]
120 pub unsafe fn bits(self, value: u8) -> &'a mut W {
121 self.w.bits = (self.w.bits & !(0x03 << 12)) | (((value as u32) & 0x03) << 12);
122 self.w
123 }
124}
125#[doc = "Reader of field `LPUART1SEL`"]
126pub type LPUART1SEL_R = crate::R<u8, u8>;
127#[doc = "Write proxy for field `LPUART1SEL`"]
128pub struct LPUART1SEL_W<'a> {
129 w: &'a mut W,
130}
131impl<'a> LPUART1SEL_W<'a> {
132 #[doc = r"Writes raw bits to the field"]
133 #[inline(always)]
134 pub unsafe fn bits(self, value: u8) -> &'a mut W {
135 self.w.bits = (self.w.bits & !(0x03 << 10)) | (((value as u32) & 0x03) << 10);
136 self.w
137 }
138}
139#[doc = "Reader of field `USART1SEL`"]
140pub type USART1SEL_R = crate::R<u8, u8>;
141#[doc = "Write proxy for field `USART1SEL`"]
142pub struct USART1SEL_W<'a> {
143 w: &'a mut W,
144}
145impl<'a> USART1SEL_W<'a> {
146 #[doc = r"Writes raw bits to the field"]
147 #[inline(always)]
148 pub unsafe fn bits(self, value: u8) -> &'a mut W {
149 self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
150 self.w
151 }
152}
153impl R {
154 #[doc = "Bits 30:31 - RNG clock source selection"]
155 #[inline(always)]
156 pub fn rngsel(&self) -> RNGSEL_R {
157 RNGSEL_R::new(((self.bits >> 30) & 0x03) as u8)
158 }
159 #[doc = "Bits 28:29 - ADCs clock source selection"]
160 #[inline(always)]
161 pub fn adcsel(&self) -> ADCSEL_R {
162 ADCSEL_R::new(((self.bits >> 28) & 0x03) as u8)
163 }
164 #[doc = "Bits 26:27 - 48 MHz clock source selection"]
165 #[inline(always)]
166 pub fn clk48sel(&self) -> CLK48SEL_R {
167 CLK48SEL_R::new(((self.bits >> 26) & 0x03) as u8)
168 }
169 #[doc = "Bits 22:23 - SAI1 clock source selection"]
170 #[inline(always)]
171 pub fn sai1sel(&self) -> SAI1SEL_R {
172 SAI1SEL_R::new(((self.bits >> 22) & 0x03) as u8)
173 }
174 #[doc = "Bits 20:21 - Low power timer 2 clock source selection"]
175 #[inline(always)]
176 pub fn lptim2sel(&self) -> LPTIM2SEL_R {
177 LPTIM2SEL_R::new(((self.bits >> 20) & 0x03) as u8)
178 }
179 #[doc = "Bits 18:19 - Low power timer 1 clock source selection"]
180 #[inline(always)]
181 pub fn lptim1sel(&self) -> LPTIM1SEL_R {
182 LPTIM1SEL_R::new(((self.bits >> 18) & 0x03) as u8)
183 }
184 #[doc = "Bits 16:17 - I2C3 clock source selection"]
185 #[inline(always)]
186 pub fn i2c3sel(&self) -> I2C3SEL_R {
187 I2C3SEL_R::new(((self.bits >> 16) & 0x03) as u8)
188 }
189 #[doc = "Bits 12:13 - I2C1 clock source selection"]
190 #[inline(always)]
191 pub fn i2c1sel(&self) -> I2C1SEL_R {
192 I2C1SEL_R::new(((self.bits >> 12) & 0x03) as u8)
193 }
194 #[doc = "Bits 10:11 - LPUART1 clock source selection"]
195 #[inline(always)]
196 pub fn lpuart1sel(&self) -> LPUART1SEL_R {
197 LPUART1SEL_R::new(((self.bits >> 10) & 0x03) as u8)
198 }
199 #[doc = "Bits 0:1 - USART1 clock source selection"]
200 #[inline(always)]
201 pub fn usart1sel(&self) -> USART1SEL_R {
202 USART1SEL_R::new((self.bits & 0x03) as u8)
203 }
204}
205impl W {
206 #[doc = "Bits 30:31 - RNG clock source selection"]
207 #[inline(always)]
208 pub fn rngsel(&mut self) -> RNGSEL_W {
209 RNGSEL_W { w: self }
210 }
211 #[doc = "Bits 28:29 - ADCs clock source selection"]
212 #[inline(always)]
213 pub fn adcsel(&mut self) -> ADCSEL_W {
214 ADCSEL_W { w: self }
215 }
216 #[doc = "Bits 26:27 - 48 MHz clock source selection"]
217 #[inline(always)]
218 pub fn clk48sel(&mut self) -> CLK48SEL_W {
219 CLK48SEL_W { w: self }
220 }
221 #[doc = "Bits 22:23 - SAI1 clock source selection"]
222 #[inline(always)]
223 pub fn sai1sel(&mut self) -> SAI1SEL_W {
224 SAI1SEL_W { w: self }
225 }
226 #[doc = "Bits 20:21 - Low power timer 2 clock source selection"]
227 #[inline(always)]
228 pub fn lptim2sel(&mut self) -> LPTIM2SEL_W {
229 LPTIM2SEL_W { w: self }
230 }
231 #[doc = "Bits 18:19 - Low power timer 1 clock source selection"]
232 #[inline(always)]
233 pub fn lptim1sel(&mut self) -> LPTIM1SEL_W {
234 LPTIM1SEL_W { w: self }
235 }
236 #[doc = "Bits 16:17 - I2C3 clock source selection"]
237 #[inline(always)]
238 pub fn i2c3sel(&mut self) -> I2C3SEL_W {
239 I2C3SEL_W { w: self }
240 }
241 #[doc = "Bits 12:13 - I2C1 clock source selection"]
242 #[inline(always)]
243 pub fn i2c1sel(&mut self) -> I2C1SEL_W {
244 I2C1SEL_W { w: self }
245 }
246 #[doc = "Bits 10:11 - LPUART1 clock source selection"]
247 #[inline(always)]
248 pub fn lpuart1sel(&mut self) -> LPUART1SEL_W {
249 LPUART1SEL_W { w: self }
250 }
251 #[doc = "Bits 0:1 - USART1 clock source selection"]
252 #[inline(always)]
253 pub fn usart1sel(&mut self) -> USART1SEL_W {
254 USART1SEL_W { w: self }
255 }
256}