stm32wb_pac/rcc/
c2apb2smenr.rs

1#[doc = "Reader of register C2APB2SMENR"]
2pub type R = crate::R<u32, super::C2APB2SMENR>;
3#[doc = "Writer for register C2APB2SMENR"]
4pub type W = crate::W<u32, super::C2APB2SMENR>;
5#[doc = "Register C2APB2SMENR `reset()`'s with value 0x0026_5800"]
6impl crate::ResetValue for super::C2APB2SMENR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0026_5800
11    }
12}
13#[doc = "Reader of field `SAI1SMEN`"]
14pub type SAI1SMEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `SAI1SMEN`"]
16pub struct SAI1SMEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> SAI1SMEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
34        self.w
35    }
36}
37#[doc = "Reader of field `TIM17SMEN`"]
38pub type TIM17SMEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `TIM17SMEN`"]
40pub struct TIM17SMEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> TIM17SMEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
58        self.w
59    }
60}
61#[doc = "Reader of field `TIM16SMEN`"]
62pub type TIM16SMEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `TIM16SMEN`"]
64pub struct TIM16SMEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> TIM16SMEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
82        self.w
83    }
84}
85#[doc = "Reader of field `USART1SMEN`"]
86pub type USART1SMEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `USART1SMEN`"]
88pub struct USART1SMEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> USART1SMEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14);
106        self.w
107    }
108}
109#[doc = "Reader of field `SPI1SMEN`"]
110pub type SPI1SMEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `SPI1SMEN`"]
112pub struct SPI1SMEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> SPI1SMEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
130        self.w
131    }
132}
133#[doc = "Reader of field `TIM1SMEN`"]
134pub type TIM1SMEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `TIM1SMEN`"]
136pub struct TIM1SMEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> TIM1SMEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
154        self.w
155    }
156}
157impl R {
158    #[doc = "Bit 21 - SAI1 clocks enable during CPU2 Sleep mode"]
159    #[inline(always)]
160    pub fn sai1smen(&self) -> SAI1SMEN_R {
161        SAI1SMEN_R::new(((self.bits >> 21) & 0x01) != 0)
162    }
163    #[doc = "Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode"]
164    #[inline(always)]
165    pub fn tim17smen(&self) -> TIM17SMEN_R {
166        TIM17SMEN_R::new(((self.bits >> 18) & 0x01) != 0)
167    }
168    #[doc = "Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode"]
169    #[inline(always)]
170    pub fn tim16smen(&self) -> TIM16SMEN_R {
171        TIM16SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
172    }
173    #[doc = "Bit 14 - USART1clocks enable during CPU2 Sleep mode"]
174    #[inline(always)]
175    pub fn usart1smen(&self) -> USART1SMEN_R {
176        USART1SMEN_R::new(((self.bits >> 14) & 0x01) != 0)
177    }
178    #[doc = "Bit 12 - SPI1 clocks enable during CPU2 Sleep mode"]
179    #[inline(always)]
180    pub fn spi1smen(&self) -> SPI1SMEN_R {
181        SPI1SMEN_R::new(((self.bits >> 12) & 0x01) != 0)
182    }
183    #[doc = "Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode"]
184    #[inline(always)]
185    pub fn tim1smen(&self) -> TIM1SMEN_R {
186        TIM1SMEN_R::new(((self.bits >> 11) & 0x01) != 0)
187    }
188}
189impl W {
190    #[doc = "Bit 21 - SAI1 clocks enable during CPU2 Sleep mode"]
191    #[inline(always)]
192    pub fn sai1smen(&mut self) -> SAI1SMEN_W {
193        SAI1SMEN_W { w: self }
194    }
195    #[doc = "Bit 18 - TIM17 timer clocks enable during CPU2 Sleep mode"]
196    #[inline(always)]
197    pub fn tim17smen(&mut self) -> TIM17SMEN_W {
198        TIM17SMEN_W { w: self }
199    }
200    #[doc = "Bit 17 - TIM16 timer clocks enable during CPU2 Sleep mode"]
201    #[inline(always)]
202    pub fn tim16smen(&mut self) -> TIM16SMEN_W {
203        TIM16SMEN_W { w: self }
204    }
205    #[doc = "Bit 14 - USART1clocks enable during CPU2 Sleep mode"]
206    #[inline(always)]
207    pub fn usart1smen(&mut self) -> USART1SMEN_W {
208        USART1SMEN_W { w: self }
209    }
210    #[doc = "Bit 12 - SPI1 clocks enable during CPU2 Sleep mode"]
211    #[inline(always)]
212    pub fn spi1smen(&mut self) -> SPI1SMEN_W {
213        SPI1SMEN_W { w: self }
214    }
215    #[doc = "Bit 11 - TIM1 timer clocks enable during CPU2 Sleep mode"]
216    #[inline(always)]
217    pub fn tim1smen(&mut self) -> TIM1SMEN_W {
218        TIM1SMEN_W { w: self }
219    }
220}
stm32wb_pac/rcc/c2apb2smenr.rs

stm32wb_pac/rcc/
c2apb2smenr.rs
