stm32wb_pac/rcc/
c2ahb2enr.rs

1#[doc = "Reader of register C2AHB2ENR"]
2pub type R = crate::R<u32, super::C2AHB2ENR>;
3#[doc = "Writer for register C2AHB2ENR"]
4pub type W = crate::W<u32, super::C2AHB2ENR>;
5#[doc = "Register C2AHB2ENR `reset()`'s with value 0"]
6impl crate::ResetValue for super::C2AHB2ENR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `AES1EN`"]
14pub type AES1EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `AES1EN`"]
16pub struct AES1EN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> AES1EN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
34        self.w
35    }
36}
37#[doc = "Reader of field `ADCEN`"]
38pub type ADCEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `ADCEN`"]
40pub struct ADCEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> ADCEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
58        self.w
59    }
60}
61#[doc = "Reader of field `GPIOHEN`"]
62pub type GPIOHEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `GPIOHEN`"]
64pub struct GPIOHEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> GPIOHEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
82        self.w
83    }
84}
85#[doc = "Reader of field `GPIOEEN`"]
86pub type GPIOEEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `GPIOEEN`"]
88pub struct GPIOEEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> GPIOEEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
106        self.w
107    }
108}
109#[doc = "Reader of field `GPIODEN`"]
110pub type GPIODEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `GPIODEN`"]
112pub struct GPIODEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> GPIODEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
130        self.w
131    }
132}
133#[doc = "Reader of field `GPIOCEN`"]
134pub type GPIOCEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `GPIOCEN`"]
136pub struct GPIOCEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> GPIOCEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
154        self.w
155    }
156}
157#[doc = "Reader of field `GPIOBEN`"]
158pub type GPIOBEN_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `GPIOBEN`"]
160pub struct GPIOBEN_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> GPIOBEN_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
178        self.w
179    }
180}
181#[doc = "Reader of field `GPIOAEN`"]
182pub type GPIOAEN_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `GPIOAEN`"]
184pub struct GPIOAEN_W<'a> {
185    w: &'a mut W,
186}
187impl<'a> GPIOAEN_W<'a> {
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
202        self.w
203    }
204}
205impl R {
206    #[doc = "Bit 16 - CPU2 AES1 accelerator clock enable"]
207    #[inline(always)]
208    pub fn aes1en(&self) -> AES1EN_R {
209        AES1EN_R::new(((self.bits >> 16) & 0x01) != 0)
210    }
211    #[doc = "Bit 13 - CPU2 ADC clock enable"]
212    #[inline(always)]
213    pub fn adcen(&self) -> ADCEN_R {
214        ADCEN_R::new(((self.bits >> 13) & 0x01) != 0)
215    }
216    #[doc = "Bit 7 - CPU2 IO port H clock enable"]
217    #[inline(always)]
218    pub fn gpiohen(&self) -> GPIOHEN_R {
219        GPIOHEN_R::new(((self.bits >> 7) & 0x01) != 0)
220    }
221    #[doc = "Bit 4 - CPU2 IO port E clock enable"]
222    #[inline(always)]
223    pub fn gpioeen(&self) -> GPIOEEN_R {
224        GPIOEEN_R::new(((self.bits >> 4) & 0x01) != 0)
225    }
226    #[doc = "Bit 3 - CPU2 IO port D clock enable"]
227    #[inline(always)]
228    pub fn gpioden(&self) -> GPIODEN_R {
229        GPIODEN_R::new(((self.bits >> 3) & 0x01) != 0)
230    }
231    #[doc = "Bit 2 - CPU2 IO port C clock enable"]
232    #[inline(always)]
233    pub fn gpiocen(&self) -> GPIOCEN_R {
234        GPIOCEN_R::new(((self.bits >> 2) & 0x01) != 0)
235    }
236    #[doc = "Bit 1 - CPU2 IO port B clock enable"]
237    #[inline(always)]
238    pub fn gpioben(&self) -> GPIOBEN_R {
239        GPIOBEN_R::new(((self.bits >> 1) & 0x01) != 0)
240    }
241    #[doc = "Bit 0 - CPU2 IO port A clock enable"]
242    #[inline(always)]
243    pub fn gpioaen(&self) -> GPIOAEN_R {
244        GPIOAEN_R::new((self.bits & 0x01) != 0)
245    }
246}
247impl W {
248    #[doc = "Bit 16 - CPU2 AES1 accelerator clock enable"]
249    #[inline(always)]
250    pub fn aes1en(&mut self) -> AES1EN_W {
251        AES1EN_W { w: self }
252    }
253    #[doc = "Bit 13 - CPU2 ADC clock enable"]
254    #[inline(always)]
255    pub fn adcen(&mut self) -> ADCEN_W {
256        ADCEN_W { w: self }
257    }
258    #[doc = "Bit 7 - CPU2 IO port H clock enable"]
259    #[inline(always)]
260    pub fn gpiohen(&mut self) -> GPIOHEN_W {
261        GPIOHEN_W { w: self }
262    }
263    #[doc = "Bit 4 - CPU2 IO port E clock enable"]
264    #[inline(always)]
265    pub fn gpioeen(&mut self) -> GPIOEEN_W {
266        GPIOEEN_W { w: self }
267    }
268    #[doc = "Bit 3 - CPU2 IO port D clock enable"]
269    #[inline(always)]
270    pub fn gpioden(&mut self) -> GPIODEN_W {
271        GPIODEN_W { w: self }
272    }
273    #[doc = "Bit 2 - CPU2 IO port C clock enable"]
274    #[inline(always)]
275    pub fn gpiocen(&mut self) -> GPIOCEN_W {
276        GPIOCEN_W { w: self }
277    }
278    #[doc = "Bit 1 - CPU2 IO port B clock enable"]
279    #[inline(always)]
280    pub fn gpioben(&mut self) -> GPIOBEN_W {
281        GPIOBEN_W { w: self }
282    }
283    #[doc = "Bit 0 - CPU2 IO port A clock enable"]
284    #[inline(always)]
285    pub fn gpioaen(&mut self) -> GPIOAEN_W {
286        GPIOAEN_W { w: self }
287    }
288}
stm32wb_pac/rcc/c2ahb2enr.rs

stm32wb_pac/rcc/
c2ahb2enr.rs
