stm32wb_pac/rcc/
c2ahb1smenr.rs

1#[doc = "Reader of register C2AHB1SMENR"]
2pub type R = crate::R<u32, super::C2AHB1SMENR>;
3#[doc = "Writer for register C2AHB1SMENR"]
4pub type W = crate::W<u32, super::C2AHB1SMENR>;
5#[doc = "Register C2AHB1SMENR `reset()`'s with value 0x0001_1207"]
6impl crate::ResetValue for super::C2AHB1SMENR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0001_1207
11    }
12}
13#[doc = "Reader of field `TSCSMEN`"]
14pub type TSCSMEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `TSCSMEN`"]
16pub struct TSCSMEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> TSCSMEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
34        self.w
35    }
36}
37#[doc = "Reader of field `CRCSMEN`"]
38pub type CRCSMEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `CRCSMEN`"]
40pub struct CRCSMEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> CRCSMEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
58        self.w
59    }
60}
61#[doc = "Reader of field `SRAM1SMEN`"]
62pub type SRAM1SMEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `SRAM1SMEN`"]
64pub struct SRAM1SMEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> SRAM1SMEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
82        self.w
83    }
84}
85#[doc = "Reader of field `DMAMUXSMEN`"]
86pub type DMAMUXSMEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DMAMUXSMEN`"]
88pub struct DMAMUXSMEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DMAMUXSMEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
106        self.w
107    }
108}
109#[doc = "Reader of field `DMA2SMEN`"]
110pub type DMA2SMEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `DMA2SMEN`"]
112pub struct DMA2SMEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> DMA2SMEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
130        self.w
131    }
132}
133#[doc = "Reader of field `DMA1SMEN`"]
134pub type DMA1SMEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `DMA1SMEN`"]
136pub struct DMA1SMEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> DMA1SMEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
154        self.w
155    }
156}
157impl R {
158    #[doc = "Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes"]
159    #[inline(always)]
160    pub fn tscsmen(&self) -> TSCSMEN_R {
161        TSCSMEN_R::new(((self.bits >> 16) & 0x01) != 0)
162    }
163    #[doc = "Bit 12 - CPU2 CRCSMEN"]
164    #[inline(always)]
165    pub fn crcsmen(&self) -> CRCSMEN_R {
166        CRCSMEN_R::new(((self.bits >> 12) & 0x01) != 0)
167    }
168    #[doc = "Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode"]
169    #[inline(always)]
170    pub fn sram1smen(&self) -> SRAM1SMEN_R {
171        SRAM1SMEN_R::new(((self.bits >> 9) & 0x01) != 0)
172    }
173    #[doc = "Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes"]
174    #[inline(always)]
175    pub fn dmamuxsmen(&self) -> DMAMUXSMEN_R {
176        DMAMUXSMEN_R::new(((self.bits >> 2) & 0x01) != 0)
177    }
178    #[doc = "Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes"]
179    #[inline(always)]
180    pub fn dma2smen(&self) -> DMA2SMEN_R {
181        DMA2SMEN_R::new(((self.bits >> 1) & 0x01) != 0)
182    }
183    #[doc = "Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes"]
184    #[inline(always)]
185    pub fn dma1smen(&self) -> DMA1SMEN_R {
186        DMA1SMEN_R::new((self.bits & 0x01) != 0)
187    }
188}
189impl W {
190    #[doc = "Bit 16 - CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes"]
191    #[inline(always)]
192    pub fn tscsmen(&mut self) -> TSCSMEN_W {
193        TSCSMEN_W { w: self }
194    }
195    #[doc = "Bit 12 - CPU2 CRCSMEN"]
196    #[inline(always)]
197    pub fn crcsmen(&mut self) -> CRCSMEN_W {
198        CRCSMEN_W { w: self }
199    }
200    #[doc = "Bit 9 - SRAM1 interface clock enable during CPU1 CSleep mode"]
201    #[inline(always)]
202    pub fn sram1smen(&mut self) -> SRAM1SMEN_W {
203        SRAM1SMEN_W { w: self }
204    }
205    #[doc = "Bit 2 - CPU2 DMAMUX clocks enable during Sleep and Stop modes"]
206    #[inline(always)]
207    pub fn dmamuxsmen(&mut self) -> DMAMUXSMEN_W {
208        DMAMUXSMEN_W { w: self }
209    }
210    #[doc = "Bit 1 - CPU2 DMA2 clocks enable during Sleep and Stop modes"]
211    #[inline(always)]
212    pub fn dma2smen(&mut self) -> DMA2SMEN_W {
213        DMA2SMEN_W { w: self }
214    }
215    #[doc = "Bit 0 - CPU2 DMA1 clocks enable during Sleep and Stop modes"]
216    #[inline(always)]
217    pub fn dma1smen(&mut self) -> DMA1SMEN_W {
218        DMA1SMEN_W { w: self }
219    }
220}
stm32wb_pac/rcc/c2ahb1smenr.rs

stm32wb_pac/rcc/
c2ahb1smenr.rs
