1#[doc = "Reader of register BDCR"]
2pub type R = crate::R<u32, super::BDCR>;
3#[doc = "Writer for register BDCR"]
4pub type W = crate::W<u32, super::BDCR>;
5#[doc = "Register BDCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::BDCR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `LSCOSEL`"]
14pub type LSCOSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `LSCOSEL`"]
16pub struct LSCOSEL_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> LSCOSEL_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
24 self.w
25 }
26}
27#[doc = "Reader of field `LSCOEN`"]
28pub type LSCOEN_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `LSCOEN`"]
30pub struct LSCOEN_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> LSCOEN_W<'a> {
34 #[doc = r"Sets the field bit"]
35 #[inline(always)]
36 pub fn set_bit(self) -> &'a mut W {
37 self.bit(true)
38 }
39 #[doc = r"Clears the field bit"]
40 #[inline(always)]
41 pub fn clear_bit(self) -> &'a mut W {
42 self.bit(false)
43 }
44 #[doc = r"Writes raw bits to the field"]
45 #[inline(always)]
46 pub fn bit(self, value: bool) -> &'a mut W {
47 self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
48 self.w
49 }
50}
51#[doc = "Reader of field `BDRST`"]
52pub type BDRST_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `BDRST`"]
54pub struct BDRST_W<'a> {
55 w: &'a mut W,
56}
57impl<'a> BDRST_W<'a> {
58 #[doc = r"Sets the field bit"]
59 #[inline(always)]
60 pub fn set_bit(self) -> &'a mut W {
61 self.bit(true)
62 }
63 #[doc = r"Clears the field bit"]
64 #[inline(always)]
65 pub fn clear_bit(self) -> &'a mut W {
66 self.bit(false)
67 }
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub fn bit(self, value: bool) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
72 self.w
73 }
74}
75#[doc = "Reader of field `RTCEN`"]
76pub type RTCEN_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `RTCEN`"]
78pub struct RTCEN_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> RTCEN_W<'a> {
82 #[doc = r"Sets the field bit"]
83 #[inline(always)]
84 pub fn set_bit(self) -> &'a mut W {
85 self.bit(true)
86 }
87 #[doc = r"Clears the field bit"]
88 #[inline(always)]
89 pub fn clear_bit(self) -> &'a mut W {
90 self.bit(false)
91 }
92 #[doc = r"Writes raw bits to the field"]
93 #[inline(always)]
94 pub fn bit(self, value: bool) -> &'a mut W {
95 self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
96 self.w
97 }
98}
99#[doc = "Reader of field `RTCSEL`"]
100pub type RTCSEL_R = crate::R<u8, u8>;
101#[doc = "Write proxy for field `RTCSEL`"]
102pub struct RTCSEL_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> RTCSEL_W<'a> {
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub unsafe fn bits(self, value: u8) -> &'a mut W {
109 self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
110 self.w
111 }
112}
113#[doc = "Reader of field `LSECSSD_`"]
114pub type LSECSSD__R = crate::R<bool, bool>;
115#[doc = "Reader of field `LSECSSON`"]
116pub type LSECSSON_R = crate::R<bool, bool>;
117#[doc = "Write proxy for field `LSECSSON`"]
118pub struct LSECSSON_W<'a> {
119 w: &'a mut W,
120}
121impl<'a> LSECSSON_W<'a> {
122 #[doc = r"Sets the field bit"]
123 #[inline(always)]
124 pub fn set_bit(self) -> &'a mut W {
125 self.bit(true)
126 }
127 #[doc = r"Clears the field bit"]
128 #[inline(always)]
129 pub fn clear_bit(self) -> &'a mut W {
130 self.bit(false)
131 }
132 #[doc = r"Writes raw bits to the field"]
133 #[inline(always)]
134 pub fn bit(self, value: bool) -> &'a mut W {
135 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
136 self.w
137 }
138}
139#[doc = "Reader of field `LSEDRV`"]
140pub type LSEDRV_R = crate::R<u8, u8>;
141#[doc = "Write proxy for field `LSEDRV`"]
142pub struct LSEDRV_W<'a> {
143 w: &'a mut W,
144}
145impl<'a> LSEDRV_W<'a> {
146 #[doc = r"Writes raw bits to the field"]
147 #[inline(always)]
148 pub unsafe fn bits(self, value: u8) -> &'a mut W {
149 self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u32) & 0x03) << 3);
150 self.w
151 }
152}
153#[doc = "Reader of field `LSEBYP`"]
154pub type LSEBYP_R = crate::R<bool, bool>;
155#[doc = "Write proxy for field `LSEBYP`"]
156pub struct LSEBYP_W<'a> {
157 w: &'a mut W,
158}
159impl<'a> LSEBYP_W<'a> {
160 #[doc = r"Sets the field bit"]
161 #[inline(always)]
162 pub fn set_bit(self) -> &'a mut W {
163 self.bit(true)
164 }
165 #[doc = r"Clears the field bit"]
166 #[inline(always)]
167 pub fn clear_bit(self) -> &'a mut W {
168 self.bit(false)
169 }
170 #[doc = r"Writes raw bits to the field"]
171 #[inline(always)]
172 pub fn bit(self, value: bool) -> &'a mut W {
173 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
174 self.w
175 }
176}
177#[doc = "Reader of field `LSERDY`"]
178pub type LSERDY_R = crate::R<bool, bool>;
179#[doc = "Reader of field `LSEON`"]
180pub type LSEON_R = crate::R<bool, bool>;
181#[doc = "Write proxy for field `LSEON`"]
182pub struct LSEON_W<'a> {
183 w: &'a mut W,
184}
185impl<'a> LSEON_W<'a> {
186 #[doc = r"Sets the field bit"]
187 #[inline(always)]
188 pub fn set_bit(self) -> &'a mut W {
189 self.bit(true)
190 }
191 #[doc = r"Clears the field bit"]
192 #[inline(always)]
193 pub fn clear_bit(self) -> &'a mut W {
194 self.bit(false)
195 }
196 #[doc = r"Writes raw bits to the field"]
197 #[inline(always)]
198 pub fn bit(self, value: bool) -> &'a mut W {
199 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
200 self.w
201 }
202}
203impl R {
204 #[doc = "Bits 25:26 - Low speed clock output selection"]
205 #[inline(always)]
206 pub fn lscosel(&self) -> LSCOSEL_R {
207 LSCOSEL_R::new(((self.bits >> 25) & 0x03) as u8)
208 }
209 #[doc = "Bit 24 - Low speed clock output enable"]
210 #[inline(always)]
211 pub fn lscoen(&self) -> LSCOEN_R {
212 LSCOEN_R::new(((self.bits >> 24) & 0x01) != 0)
213 }
214 #[doc = "Bit 16 - Backup domain software reset"]
215 #[inline(always)]
216 pub fn bdrst(&self) -> BDRST_R {
217 BDRST_R::new(((self.bits >> 16) & 0x01) != 0)
218 }
219 #[doc = "Bit 15 - RTC clock enable"]
220 #[inline(always)]
221 pub fn rtcen(&self) -> RTCEN_R {
222 RTCEN_R::new(((self.bits >> 15) & 0x01) != 0)
223 }
224 #[doc = "Bits 8:9 - RTC clock source selection"]
225 #[inline(always)]
226 pub fn rtcsel(&self) -> RTCSEL_R {
227 RTCSEL_R::new(((self.bits >> 8) & 0x03) as u8)
228 }
229 #[doc = "Bit 6 - CSS on LSE failure detection"]
230 #[inline(always)]
231 pub fn lsecssd_(&self) -> LSECSSD__R {
232 LSECSSD__R::new(((self.bits >> 6) & 0x01) != 0)
233 }
234 #[doc = "Bit 5 - LSECSSON"]
235 #[inline(always)]
236 pub fn lsecsson(&self) -> LSECSSON_R {
237 LSECSSON_R::new(((self.bits >> 5) & 0x01) != 0)
238 }
239 #[doc = "Bits 3:4 - SE oscillator drive capability"]
240 #[inline(always)]
241 pub fn lsedrv(&self) -> LSEDRV_R {
242 LSEDRV_R::new(((self.bits >> 3) & 0x03) as u8)
243 }
244 #[doc = "Bit 2 - LSE oscillator bypass"]
245 #[inline(always)]
246 pub fn lsebyp(&self) -> LSEBYP_R {
247 LSEBYP_R::new(((self.bits >> 2) & 0x01) != 0)
248 }
249 #[doc = "Bit 1 - LSE oscillator ready"]
250 #[inline(always)]
251 pub fn lserdy(&self) -> LSERDY_R {
252 LSERDY_R::new(((self.bits >> 1) & 0x01) != 0)
253 }
254 #[doc = "Bit 0 - LSE oscillator enable"]
255 #[inline(always)]
256 pub fn lseon(&self) -> LSEON_R {
257 LSEON_R::new((self.bits & 0x01) != 0)
258 }
259}
260impl W {
261 #[doc = "Bits 25:26 - Low speed clock output selection"]
262 #[inline(always)]
263 pub fn lscosel(&mut self) -> LSCOSEL_W {
264 LSCOSEL_W { w: self }
265 }
266 #[doc = "Bit 24 - Low speed clock output enable"]
267 #[inline(always)]
268 pub fn lscoen(&mut self) -> LSCOEN_W {
269 LSCOEN_W { w: self }
270 }
271 #[doc = "Bit 16 - Backup domain software reset"]
272 #[inline(always)]
273 pub fn bdrst(&mut self) -> BDRST_W {
274 BDRST_W { w: self }
275 }
276 #[doc = "Bit 15 - RTC clock enable"]
277 #[inline(always)]
278 pub fn rtcen(&mut self) -> RTCEN_W {
279 RTCEN_W { w: self }
280 }
281 #[doc = "Bits 8:9 - RTC clock source selection"]
282 #[inline(always)]
283 pub fn rtcsel(&mut self) -> RTCSEL_W {
284 RTCSEL_W { w: self }
285 }
286 #[doc = "Bit 5 - LSECSSON"]
287 #[inline(always)]
288 pub fn lsecsson(&mut self) -> LSECSSON_W {
289 LSECSSON_W { w: self }
290 }
291 #[doc = "Bits 3:4 - SE oscillator drive capability"]
292 #[inline(always)]
293 pub fn lsedrv(&mut self) -> LSEDRV_W {
294 LSEDRV_W { w: self }
295 }
296 #[doc = "Bit 2 - LSE oscillator bypass"]
297 #[inline(always)]
298 pub fn lsebyp(&mut self) -> LSEBYP_W {
299 LSEBYP_W { w: self }
300 }
301 #[doc = "Bit 0 - LSE oscillator enable"]
302 #[inline(always)]
303 pub fn lseon(&mut self) -> LSEON_W {
304 LSEON_W { w: self }
305 }
306}