stm32wb_pac/rcc/
ahb3smenr.rs

1#[doc = "Reader of register AHB3SMENR"]
2pub type R = crate::R<u32, super::AHB3SMENR>;
3#[doc = "Writer for register AHB3SMENR"]
4pub type W = crate::W<u32, super::AHB3SMENR>;
5#[doc = "Register AHB3SMENR `reset()`'s with value 0x0307_0100"]
6impl crate::ResetValue for super::AHB3SMENR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0307_0100
11    }
12}
13#[doc = "Reader of field `FLASHSMEN`"]
14pub type FLASHSMEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `FLASHSMEN`"]
16pub struct FLASHSMEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> FLASHSMEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
34        self.w
35    }
36}
37#[doc = "Reader of field `SRAM2SMEN`"]
38pub type SRAM2SMEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `SRAM2SMEN`"]
40pub struct SRAM2SMEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> SRAM2SMEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
58        self.w
59    }
60}
61#[doc = "Reader of field `RNGSMEN`"]
62pub type RNGSMEN_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `RNGSMEN`"]
64pub struct RNGSMEN_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> RNGSMEN_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
82        self.w
83    }
84}
85#[doc = "Reader of field `AES2SMEN`"]
86pub type AES2SMEN_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `AES2SMEN`"]
88pub struct AES2SMEN_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> AES2SMEN_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
106        self.w
107    }
108}
109#[doc = "Reader of field `PKASMEN`"]
110pub type PKASMEN_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `PKASMEN`"]
112pub struct PKASMEN_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> PKASMEN_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
130        self.w
131    }
132}
133#[doc = "Reader of field `QSPISMEN`"]
134pub type QSPISMEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `QSPISMEN`"]
136pub struct QSPISMEN_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> QSPISMEN_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
154        self.w
155    }
156}
157impl R {
158    #[doc = "Bit 25 - Flash interface clocks enable during CPU1 sleep mode"]
159    #[inline(always)]
160    pub fn flashsmen(&self) -> FLASHSMEN_R {
161        FLASHSMEN_R::new(((self.bits >> 25) & 0x01) != 0)
162    }
163    #[doc = "Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode"]
164    #[inline(always)]
165    pub fn sram2smen(&self) -> SRAM2SMEN_R {
166        SRAM2SMEN_R::new(((self.bits >> 24) & 0x01) != 0)
167    }
168    #[doc = "Bit 18 - True RNG clocks enable during CPU1 sleep mode"]
169    #[inline(always)]
170    pub fn rngsmen(&self) -> RNGSMEN_R {
171        RNGSMEN_R::new(((self.bits >> 18) & 0x01) != 0)
172    }
173    #[doc = "Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode"]
174    #[inline(always)]
175    pub fn aes2smen(&self) -> AES2SMEN_R {
176        AES2SMEN_R::new(((self.bits >> 17) & 0x01) != 0)
177    }
178    #[doc = "Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode"]
179    #[inline(always)]
180    pub fn pkasmen(&self) -> PKASMEN_R {
181        PKASMEN_R::new(((self.bits >> 16) & 0x01) != 0)
182    }
183    #[doc = "Bit 8 - QSPISMEN"]
184    #[inline(always)]
185    pub fn qspismen(&self) -> QSPISMEN_R {
186        QSPISMEN_R::new(((self.bits >> 8) & 0x01) != 0)
187    }
188}
189impl W {
190    #[doc = "Bit 25 - Flash interface clocks enable during CPU1 sleep mode"]
191    #[inline(always)]
192    pub fn flashsmen(&mut self) -> FLASHSMEN_W {
193        FLASHSMEN_W { w: self }
194    }
195    #[doc = "Bit 24 - SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode"]
196    #[inline(always)]
197    pub fn sram2smen(&mut self) -> SRAM2SMEN_W {
198        SRAM2SMEN_W { w: self }
199    }
200    #[doc = "Bit 18 - True RNG clocks enable during CPU1 sleep mode"]
201    #[inline(always)]
202    pub fn rngsmen(&mut self) -> RNGSMEN_W {
203        RNGSMEN_W { w: self }
204    }
205    #[doc = "Bit 17 - AES2 accelerator clocks enable during CPU1 sleep mode"]
206    #[inline(always)]
207    pub fn aes2smen(&mut self) -> AES2SMEN_W {
208        AES2SMEN_W { w: self }
209    }
210    #[doc = "Bit 16 - PKA accelerator clocks enable during CPU1 sleep mode"]
211    #[inline(always)]
212    pub fn pkasmen(&mut self) -> PKASMEN_W {
213        PKASMEN_W { w: self }
214    }
215    #[doc = "Bit 8 - QSPISMEN"]
216    #[inline(always)]
217    pub fn qspismen(&mut self) -> QSPISMEN_W {
218        QSPISMEN_W { w: self }
219    }
220}
stm32wb_pac/rcc/ahb3smenr.rs

stm32wb_pac/rcc/
ahb3smenr.rs
