stm32wb_pac/quadspi/
dcr.rs

1#[doc = "Reader of register DCR"]
2pub type R = crate::R<u32, super::DCR>;
3#[doc = "Writer for register DCR"]
4pub type W = crate::W<u32, super::DCR>;
5#[doc = "Register DCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::DCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `FSIZE`"]
14pub type FSIZE_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `FSIZE`"]
16pub struct FSIZE_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> FSIZE_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16);
24        self.w
25    }
26}
27#[doc = "Reader of field `CSHT`"]
28pub type CSHT_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `CSHT`"]
30pub struct CSHT_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> CSHT_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
38        self.w
39    }
40}
41#[doc = "Reader of field `CKMODE`"]
42pub type CKMODE_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `CKMODE`"]
44pub struct CKMODE_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> CKMODE_W<'a> {
48    #[doc = r"Sets the field bit"]
49    #[inline(always)]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r"Clears the field bit"]
54    #[inline(always)]
55    pub fn clear_bit(self) -> &'a mut W {
56        self.bit(false)
57    }
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub fn bit(self, value: bool) -> &'a mut W {
61        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
62        self.w
63    }
64}
65impl R {
66    #[doc = "Bits 16:20 - FLASH memory size"]
67    #[inline(always)]
68    pub fn fsize(&self) -> FSIZE_R {
69        FSIZE_R::new(((self.bits >> 16) & 0x1f) as u8)
70    }
71    #[doc = "Bits 8:10 - Chip select high time"]
72    #[inline(always)]
73    pub fn csht(&self) -> CSHT_R {
74        CSHT_R::new(((self.bits >> 8) & 0x07) as u8)
75    }
76    #[doc = "Bit 0 - Mode 0 / mode 3"]
77    #[inline(always)]
78    pub fn ckmode(&self) -> CKMODE_R {
79        CKMODE_R::new((self.bits & 0x01) != 0)
80    }
81}
82impl W {
83    #[doc = "Bits 16:20 - FLASH memory size"]
84    #[inline(always)]
85    pub fn fsize(&mut self) -> FSIZE_W {
86        FSIZE_W { w: self }
87    }
88    #[doc = "Bits 8:10 - Chip select high time"]
89    #[inline(always)]
90    pub fn csht(&mut self) -> CSHT_W {
91        CSHT_W { w: self }
92    }
93    #[doc = "Bit 0 - Mode 0 / mode 3"]
94    #[inline(always)]
95    pub fn ckmode(&mut self) -> CKMODE_W {
96        CKMODE_W { w: self }
97    }
98}
stm32wb_pac/quadspi/dcr.rs

stm32wb_pac/quadspi/
dcr.rs
