stm32wb_pac/i2c1/
timingr.rs

1#[doc = "Reader of register TIMINGR"]
2pub type R = crate::R<u32, super::TIMINGR>;
3#[doc = "Writer for register TIMINGR"]
4pub type W = crate::W<u32, super::TIMINGR>;
5#[doc = "Register TIMINGR `reset()`'s with value 0"]
6impl crate::ResetValue for super::TIMINGR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `SCLL`"]
14pub type SCLL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `SCLL`"]
16pub struct SCLL_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> SCLL_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
24        self.w
25    }
26}
27#[doc = "Reader of field `SCLH`"]
28pub type SCLH_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `SCLH`"]
30pub struct SCLH_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> SCLH_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
38        self.w
39    }
40}
41#[doc = "Reader of field `SDADEL`"]
42pub type SDADEL_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `SDADEL`"]
44pub struct SDADEL_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> SDADEL_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
52        self.w
53    }
54}
55#[doc = "Reader of field `SCLDEL`"]
56pub type SCLDEL_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `SCLDEL`"]
58pub struct SCLDEL_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> SCLDEL_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
66        self.w
67    }
68}
69#[doc = "Reader of field `PRESC`"]
70pub type PRESC_R = crate::R<u8, u8>;
71#[doc = "Write proxy for field `PRESC`"]
72pub struct PRESC_W<'a> {
73    w: &'a mut W,
74}
75impl<'a> PRESC_W<'a> {
76    #[doc = r"Writes raw bits to the field"]
77    #[inline(always)]
78    pub unsafe fn bits(self, value: u8) -> &'a mut W {
79        self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
80        self.w
81    }
82}
83impl R {
84    #[doc = "Bits 0:7 - SCL low period (master mode)"]
85    #[inline(always)]
86    pub fn scll(&self) -> SCLL_R {
87        SCLL_R::new((self.bits & 0xff) as u8)
88    }
89    #[doc = "Bits 8:15 - SCL high period (master mode)"]
90    #[inline(always)]
91    pub fn sclh(&self) -> SCLH_R {
92        SCLH_R::new(((self.bits >> 8) & 0xff) as u8)
93    }
94    #[doc = "Bits 16:19 - Data hold time"]
95    #[inline(always)]
96    pub fn sdadel(&self) -> SDADEL_R {
97        SDADEL_R::new(((self.bits >> 16) & 0x0f) as u8)
98    }
99    #[doc = "Bits 20:23 - Data setup time"]
100    #[inline(always)]
101    pub fn scldel(&self) -> SCLDEL_R {
102        SCLDEL_R::new(((self.bits >> 20) & 0x0f) as u8)
103    }
104    #[doc = "Bits 28:31 - Timing prescaler"]
105    #[inline(always)]
106    pub fn presc(&self) -> PRESC_R {
107        PRESC_R::new(((self.bits >> 28) & 0x0f) as u8)
108    }
109}
110impl W {
111    #[doc = "Bits 0:7 - SCL low period (master mode)"]
112    #[inline(always)]
113    pub fn scll(&mut self) -> SCLL_W {
114        SCLL_W { w: self }
115    }
116    #[doc = "Bits 8:15 - SCL high period (master mode)"]
117    #[inline(always)]
118    pub fn sclh(&mut self) -> SCLH_W {
119        SCLH_W { w: self }
120    }
121    #[doc = "Bits 16:19 - Data hold time"]
122    #[inline(always)]
123    pub fn sdadel(&mut self) -> SDADEL_W {
124        SDADEL_W { w: self }
125    }
126    #[doc = "Bits 20:23 - Data setup time"]
127    #[inline(always)]
128    pub fn scldel(&mut self) -> SCLDEL_W {
129        SCLDEL_W { w: self }
130    }
131    #[doc = "Bits 28:31 - Timing prescaler"]
132    #[inline(always)]
133    pub fn presc(&mut self) -> PRESC_W {
134        PRESC_W { w: self }
135    }
136}
stm32wb_pac/i2c1/timingr.rs

stm32wb_pac/i2c1/
timingr.rs
