1#[doc = "Reader of register ISR"]
2pub type R = crate::R<u32, super::ISR>;
3#[doc = "Writer for register ISR"]
4pub type W = crate::W<u32, super::ISR>;
5#[doc = "Register ISR `reset()`'s with value 0x01"]
6impl crate::ResetValue for super::ISR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x01
11 }
12}
13#[doc = "Reader of field `ADDCODE`"]
14pub type ADDCODE_R = crate::R<u8, u8>;
15#[doc = "Reader of field `DIR`"]
16pub type DIR_R = crate::R<bool, bool>;
17#[doc = "Reader of field `BUSY`"]
18pub type BUSY_R = crate::R<bool, bool>;
19#[doc = "Reader of field `ALERT`"]
20pub type ALERT_R = crate::R<bool, bool>;
21#[doc = "Reader of field `TIMEOUT`"]
22pub type TIMEOUT_R = crate::R<bool, bool>;
23#[doc = "Reader of field `PECERR`"]
24pub type PECERR_R = crate::R<bool, bool>;
25#[doc = "Reader of field `OVR`"]
26pub type OVR_R = crate::R<bool, bool>;
27#[doc = "Reader of field `ARLO`"]
28pub type ARLO_R = crate::R<bool, bool>;
29#[doc = "Reader of field `BERR`"]
30pub type BERR_R = crate::R<bool, bool>;
31#[doc = "Reader of field `TCR`"]
32pub type TCR_R = crate::R<bool, bool>;
33#[doc = "Reader of field `TC`"]
34pub type TC_R = crate::R<bool, bool>;
35#[doc = "Reader of field `STOPF`"]
36pub type STOPF_R = crate::R<bool, bool>;
37#[doc = "Reader of field `NACKF`"]
38pub type NACKF_R = crate::R<bool, bool>;
39#[doc = "Reader of field `ADDR`"]
40pub type ADDR_R = crate::R<bool, bool>;
41#[doc = "Reader of field `RXNE`"]
42pub type RXNE_R = crate::R<bool, bool>;
43#[doc = "Reader of field `TXIS`"]
44pub type TXIS_R = crate::R<bool, bool>;
45#[doc = "Write proxy for field `TXIS`"]
46pub struct TXIS_W<'a> {
47 w: &'a mut W,
48}
49impl<'a> TXIS_W<'a> {
50 #[doc = r"Sets the field bit"]
51 #[inline(always)]
52 pub fn set_bit(self) -> &'a mut W {
53 self.bit(true)
54 }
55 #[doc = r"Clears the field bit"]
56 #[inline(always)]
57 pub fn clear_bit(self) -> &'a mut W {
58 self.bit(false)
59 }
60 #[doc = r"Writes raw bits to the field"]
61 #[inline(always)]
62 pub fn bit(self, value: bool) -> &'a mut W {
63 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
64 self.w
65 }
66}
67#[doc = "Reader of field `TXE`"]
68pub type TXE_R = crate::R<bool, bool>;
69#[doc = "Write proxy for field `TXE`"]
70pub struct TXE_W<'a> {
71 w: &'a mut W,
72}
73impl<'a> TXE_W<'a> {
74 #[doc = r"Sets the field bit"]
75 #[inline(always)]
76 pub fn set_bit(self) -> &'a mut W {
77 self.bit(true)
78 }
79 #[doc = r"Clears the field bit"]
80 #[inline(always)]
81 pub fn clear_bit(self) -> &'a mut W {
82 self.bit(false)
83 }
84 #[doc = r"Writes raw bits to the field"]
85 #[inline(always)]
86 pub fn bit(self, value: bool) -> &'a mut W {
87 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88 self.w
89 }
90}
91impl R {
92 #[doc = "Bits 17:23 - Address match code (Slave mode)"]
93 #[inline(always)]
94 pub fn addcode(&self) -> ADDCODE_R {
95 ADDCODE_R::new(((self.bits >> 17) & 0x7f) as u8)
96 }
97 #[doc = "Bit 16 - Transfer direction (Slave mode)"]
98 #[inline(always)]
99 pub fn dir(&self) -> DIR_R {
100 DIR_R::new(((self.bits >> 16) & 0x01) != 0)
101 }
102 #[doc = "Bit 15 - Bus busy"]
103 #[inline(always)]
104 pub fn busy(&self) -> BUSY_R {
105 BUSY_R::new(((self.bits >> 15) & 0x01) != 0)
106 }
107 #[doc = "Bit 13 - SMBus alert"]
108 #[inline(always)]
109 pub fn alert(&self) -> ALERT_R {
110 ALERT_R::new(((self.bits >> 13) & 0x01) != 0)
111 }
112 #[doc = "Bit 12 - Timeout or t_low detection flag"]
113 #[inline(always)]
114 pub fn timeout(&self) -> TIMEOUT_R {
115 TIMEOUT_R::new(((self.bits >> 12) & 0x01) != 0)
116 }
117 #[doc = "Bit 11 - PEC Error in reception"]
118 #[inline(always)]
119 pub fn pecerr(&self) -> PECERR_R {
120 PECERR_R::new(((self.bits >> 11) & 0x01) != 0)
121 }
122 #[doc = "Bit 10 - Overrun/Underrun (slave mode)"]
123 #[inline(always)]
124 pub fn ovr(&self) -> OVR_R {
125 OVR_R::new(((self.bits >> 10) & 0x01) != 0)
126 }
127 #[doc = "Bit 9 - Arbitration lost"]
128 #[inline(always)]
129 pub fn arlo(&self) -> ARLO_R {
130 ARLO_R::new(((self.bits >> 9) & 0x01) != 0)
131 }
132 #[doc = "Bit 8 - Bus error"]
133 #[inline(always)]
134 pub fn berr(&self) -> BERR_R {
135 BERR_R::new(((self.bits >> 8) & 0x01) != 0)
136 }
137 #[doc = "Bit 7 - Transfer Complete Reload"]
138 #[inline(always)]
139 pub fn tcr(&self) -> TCR_R {
140 TCR_R::new(((self.bits >> 7) & 0x01) != 0)
141 }
142 #[doc = "Bit 6 - Transfer Complete (master mode)"]
143 #[inline(always)]
144 pub fn tc(&self) -> TC_R {
145 TC_R::new(((self.bits >> 6) & 0x01) != 0)
146 }
147 #[doc = "Bit 5 - Stop detection flag"]
148 #[inline(always)]
149 pub fn stopf(&self) -> STOPF_R {
150 STOPF_R::new(((self.bits >> 5) & 0x01) != 0)
151 }
152 #[doc = "Bit 4 - Not acknowledge received flag"]
153 #[inline(always)]
154 pub fn nackf(&self) -> NACKF_R {
155 NACKF_R::new(((self.bits >> 4) & 0x01) != 0)
156 }
157 #[doc = "Bit 3 - Address matched (slave mode)"]
158 #[inline(always)]
159 pub fn addr(&self) -> ADDR_R {
160 ADDR_R::new(((self.bits >> 3) & 0x01) != 0)
161 }
162 #[doc = "Bit 2 - Receive data register not empty (receivers)"]
163 #[inline(always)]
164 pub fn rxne(&self) -> RXNE_R {
165 RXNE_R::new(((self.bits >> 2) & 0x01) != 0)
166 }
167 #[doc = "Bit 1 - Transmit interrupt status (transmitters)"]
168 #[inline(always)]
169 pub fn txis(&self) -> TXIS_R {
170 TXIS_R::new(((self.bits >> 1) & 0x01) != 0)
171 }
172 #[doc = "Bit 0 - Transmit data register empty (transmitters)"]
173 #[inline(always)]
174 pub fn txe(&self) -> TXE_R {
175 TXE_R::new((self.bits & 0x01) != 0)
176 }
177}
178impl W {
179 #[doc = "Bit 1 - Transmit interrupt status (transmitters)"]
180 #[inline(always)]
181 pub fn txis(&mut self) -> TXIS_W {
182 TXIS_W { w: self }
183 }
184 #[doc = "Bit 0 - Transmit data register empty (transmitters)"]
185 #[inline(always)]
186 pub fn txe(&mut self) -> TXE_W {
187 TXE_W { w: self }
188 }
189}