stm32wb_pac/hsem/
hwcfgr2.rs

1#[doc = "Reader of register HWCFGR2"]
2pub type R = crate::R<u32, super::HWCFGR2>;
3#[doc = "Reader of field `MASTERID4`"]
4pub type MASTERID4_R = crate::R<u8, u8>;
5#[doc = "Reader of field `MASTERID3`"]
6pub type MASTERID3_R = crate::R<u8, u8>;
7#[doc = "Reader of field `MASTERID2`"]
8pub type MASTERID2_R = crate::R<u8, u8>;
9#[doc = "Reader of field `MASTERID1`"]
10pub type MASTERID1_R = crate::R<u8, u8>;
11impl R {
12    #[doc = "Bits 12:15 - Hardware Configuration valid bus masters ID4"]
13    #[inline(always)]
14    pub fn masterid4(&self) -> MASTERID4_R {
15        MASTERID4_R::new(((self.bits >> 12) & 0x0f) as u8)
16    }
17    #[doc = "Bits 8:11 - Hardware Configuration valid bus masters ID3"]
18    #[inline(always)]
19    pub fn masterid3(&self) -> MASTERID3_R {
20        MASTERID3_R::new(((self.bits >> 8) & 0x0f) as u8)
21    }
22    #[doc = "Bits 4:7 - Hardware Configuration valid bus masters ID2"]
23    #[inline(always)]
24    pub fn masterid2(&self) -> MASTERID2_R {
25        MASTERID2_R::new(((self.bits >> 4) & 0x0f) as u8)
26    }
27    #[doc = "Bits 0:3 - Hardware Configuration valid bus masters ID1"]
28    #[inline(always)]
29    pub fn masterid1(&self) -> MASTERID1_R {
30        MASTERID1_R::new((self.bits & 0x0f) as u8)
31    }
32}
stm32wb_pac/hsem/hwcfgr2.rs

stm32wb_pac/hsem/
hwcfgr2.rs
