stm32wb_pac/gpioh/
lckr.rs

1#[doc = "Reader of register LCKR"]
2pub type R = crate::R<u32, super::LCKR>;
3#[doc = "Writer for register LCKR"]
4pub type W = crate::W<u32, super::LCKR>;
5#[doc = "Register LCKR `reset()`'s with value 0"]
6impl crate::ResetValue for super::LCKR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `LCKK`"]
14pub type LCKK_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `LCKK`"]
16pub struct LCKK_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> LCKK_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
34        self.w
35    }
36}
37#[doc = "Reader of field `LCK3`"]
38pub type LCK3_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `LCK3`"]
40pub struct LCK3_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> LCK3_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
58        self.w
59    }
60}
61#[doc = "Reader of field `LCK1`"]
62pub type LCK1_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `LCK1`"]
64pub struct LCK1_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> LCK1_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
82        self.w
83    }
84}
85#[doc = "Reader of field `LCK0`"]
86pub type LCK0_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `LCK0`"]
88pub struct LCK0_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> LCK0_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
106        self.w
107    }
108}
109impl R {
110    #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"]
111    #[inline(always)]
112    pub fn lckk(&self) -> LCKK_R {
113        LCKK_R::new(((self.bits >> 16) & 0x01) != 0)
114    }
115    #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"]
116    #[inline(always)]
117    pub fn lck3(&self) -> LCK3_R {
118        LCK3_R::new(((self.bits >> 3) & 0x01) != 0)
119    }
120    #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"]
121    #[inline(always)]
122    pub fn lck1(&self) -> LCK1_R {
123        LCK1_R::new(((self.bits >> 1) & 0x01) != 0)
124    }
125    #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"]
126    #[inline(always)]
127    pub fn lck0(&self) -> LCK0_R {
128        LCK0_R::new((self.bits & 0x01) != 0)
129    }
130}
131impl W {
132    #[doc = "Bit 16 - Port x lock bit y (y= 0..15)"]
133    #[inline(always)]
134    pub fn lckk(&mut self) -> LCKK_W {
135        LCKK_W { w: self }
136    }
137    #[doc = "Bit 3 - Port x lock bit y (y= 0..15)"]
138    #[inline(always)]
139    pub fn lck3(&mut self) -> LCK3_W {
140        LCK3_W { w: self }
141    }
142    #[doc = "Bit 1 - Port x lock bit y (y= 0..15)"]
143    #[inline(always)]
144    pub fn lck1(&mut self) -> LCK1_W {
145        LCK1_W { w: self }
146    }
147    #[doc = "Bit 0 - Port x lock bit y (y= 0..15)"]
148    #[inline(always)]
149    pub fn lck0(&mut self) -> LCK0_W {
150        LCK0_W { w: self }
151    }
152}
stm32wb_pac/gpioh/lckr.rs

stm32wb_pac/gpioh/
lckr.rs
