stm32wb_pac/flash/
c2acr.rs

1#[doc = "Reader of register C2ACR"]
2pub type R = crate::R<u32, super::C2ACR>;
3#[doc = "Writer for register C2ACR"]
4pub type W = crate::W<u32, super::C2ACR>;
5#[doc = "Register C2ACR `reset()`'s with value 0x0600"]
6impl crate::ResetValue for super::C2ACR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0600
11    }
12}
13#[doc = "Reader of field `PRFTEN`"]
14pub type PRFTEN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `PRFTEN`"]
16pub struct PRFTEN_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> PRFTEN_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
34        self.w
35    }
36}
37#[doc = "Reader of field `ICEN`"]
38pub type ICEN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `ICEN`"]
40pub struct ICEN_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> ICEN_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
58        self.w
59    }
60}
61#[doc = "Reader of field `ICRST`"]
62pub type ICRST_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `ICRST`"]
64pub struct ICRST_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> ICRST_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
82        self.w
83    }
84}
85#[doc = "Reader of field `PES`"]
86pub type PES_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `PES`"]
88pub struct PES_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> PES_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
106        self.w
107    }
108}
109impl R {
110    #[doc = "Bit 8 - CPU2 cortex M0 prefetch enable"]
111    #[inline(always)]
112    pub fn prften(&self) -> PRFTEN_R {
113        PRFTEN_R::new(((self.bits >> 8) & 0x01) != 0)
114    }
115    #[doc = "Bit 9 - CPU2 cortex M0 instruction cache enable"]
116    #[inline(always)]
117    pub fn icen(&self) -> ICEN_R {
118        ICEN_R::new(((self.bits >> 9) & 0x01) != 0)
119    }
120    #[doc = "Bit 11 - CPU2 cortex M0 instruction cache reset"]
121    #[inline(always)]
122    pub fn icrst(&self) -> ICRST_R {
123        ICRST_R::new(((self.bits >> 11) & 0x01) != 0)
124    }
125    #[doc = "Bit 15 - CPU2 cortex M0 program erase suspend request"]
126    #[inline(always)]
127    pub fn pes(&self) -> PES_R {
128        PES_R::new(((self.bits >> 15) & 0x01) != 0)
129    }
130}
131impl W {
132    #[doc = "Bit 8 - CPU2 cortex M0 prefetch enable"]
133    #[inline(always)]
134    pub fn prften(&mut self) -> PRFTEN_W {
135        PRFTEN_W { w: self }
136    }
137    #[doc = "Bit 9 - CPU2 cortex M0 instruction cache enable"]
138    #[inline(always)]
139    pub fn icen(&mut self) -> ICEN_W {
140        ICEN_W { w: self }
141    }
142    #[doc = "Bit 11 - CPU2 cortex M0 instruction cache reset"]
143    #[inline(always)]
144    pub fn icrst(&mut self) -> ICRST_W {
145        ICRST_W { w: self }
146    }
147    #[doc = "Bit 15 - CPU2 cortex M0 program erase suspend request"]
148    #[inline(always)]
149    pub fn pes(&mut self) -> PES_W {
150        PES_W { w: self }
151    }
152}
stm32wb_pac/flash/c2acr.rs

stm32wb_pac/flash/
c2acr.rs
