1#[doc = "Reader of register ACR"]
2pub type R = crate::R<u32, super::ACR>;
3#[doc = "Writer for register ACR"]
4pub type W = crate::W<u32, super::ACR>;
5#[doc = "Register ACR `reset()`'s with value 0x0600"]
6impl crate::ResetValue for super::ACR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0x0600
11 }
12}
13#[doc = "Reader of field `LATENCY`"]
14pub type LATENCY_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `LATENCY`"]
16pub struct LATENCY_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> LATENCY_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
24 self.w
25 }
26}
27#[doc = "Reader of field `PRFTEN`"]
28pub type PRFTEN_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `PRFTEN`"]
30pub struct PRFTEN_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> PRFTEN_W<'a> {
34 #[doc = r"Sets the field bit"]
35 #[inline(always)]
36 pub fn set_bit(self) -> &'a mut W {
37 self.bit(true)
38 }
39 #[doc = r"Clears the field bit"]
40 #[inline(always)]
41 pub fn clear_bit(self) -> &'a mut W {
42 self.bit(false)
43 }
44 #[doc = r"Writes raw bits to the field"]
45 #[inline(always)]
46 pub fn bit(self, value: bool) -> &'a mut W {
47 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
48 self.w
49 }
50}
51#[doc = "Reader of field `ICEN`"]
52pub type ICEN_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `ICEN`"]
54pub struct ICEN_W<'a> {
55 w: &'a mut W,
56}
57impl<'a> ICEN_W<'a> {
58 #[doc = r"Sets the field bit"]
59 #[inline(always)]
60 pub fn set_bit(self) -> &'a mut W {
61 self.bit(true)
62 }
63 #[doc = r"Clears the field bit"]
64 #[inline(always)]
65 pub fn clear_bit(self) -> &'a mut W {
66 self.bit(false)
67 }
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub fn bit(self, value: bool) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
72 self.w
73 }
74}
75#[doc = "Reader of field `DCEN`"]
76pub type DCEN_R = crate::R<bool, bool>;
77#[doc = "Write proxy for field `DCEN`"]
78pub struct DCEN_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> DCEN_W<'a> {
82 #[doc = r"Sets the field bit"]
83 #[inline(always)]
84 pub fn set_bit(self) -> &'a mut W {
85 self.bit(true)
86 }
87 #[doc = r"Clears the field bit"]
88 #[inline(always)]
89 pub fn clear_bit(self) -> &'a mut W {
90 self.bit(false)
91 }
92 #[doc = r"Writes raw bits to the field"]
93 #[inline(always)]
94 pub fn bit(self, value: bool) -> &'a mut W {
95 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
96 self.w
97 }
98}
99#[doc = "Reader of field `ICRST`"]
100pub type ICRST_R = crate::R<bool, bool>;
101#[doc = "Write proxy for field `ICRST`"]
102pub struct ICRST_W<'a> {
103 w: &'a mut W,
104}
105impl<'a> ICRST_W<'a> {
106 #[doc = r"Sets the field bit"]
107 #[inline(always)]
108 pub fn set_bit(self) -> &'a mut W {
109 self.bit(true)
110 }
111 #[doc = r"Clears the field bit"]
112 #[inline(always)]
113 pub fn clear_bit(self) -> &'a mut W {
114 self.bit(false)
115 }
116 #[doc = r"Writes raw bits to the field"]
117 #[inline(always)]
118 pub fn bit(self, value: bool) -> &'a mut W {
119 self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
120 self.w
121 }
122}
123#[doc = "Reader of field `DCRST`"]
124pub type DCRST_R = crate::R<bool, bool>;
125#[doc = "Write proxy for field `DCRST`"]
126pub struct DCRST_W<'a> {
127 w: &'a mut W,
128}
129impl<'a> DCRST_W<'a> {
130 #[doc = r"Sets the field bit"]
131 #[inline(always)]
132 pub fn set_bit(self) -> &'a mut W {
133 self.bit(true)
134 }
135 #[doc = r"Clears the field bit"]
136 #[inline(always)]
137 pub fn clear_bit(self) -> &'a mut W {
138 self.bit(false)
139 }
140 #[doc = r"Writes raw bits to the field"]
141 #[inline(always)]
142 pub fn bit(self, value: bool) -> &'a mut W {
143 self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
144 self.w
145 }
146}
147#[doc = "Reader of field `PES`"]
148pub type PES_R = crate::R<bool, bool>;
149#[doc = "Write proxy for field `PES`"]
150pub struct PES_W<'a> {
151 w: &'a mut W,
152}
153impl<'a> PES_W<'a> {
154 #[doc = r"Sets the field bit"]
155 #[inline(always)]
156 pub fn set_bit(self) -> &'a mut W {
157 self.bit(true)
158 }
159 #[doc = r"Clears the field bit"]
160 #[inline(always)]
161 pub fn clear_bit(self) -> &'a mut W {
162 self.bit(false)
163 }
164 #[doc = r"Writes raw bits to the field"]
165 #[inline(always)]
166 pub fn bit(self, value: bool) -> &'a mut W {
167 self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
168 self.w
169 }
170}
171#[doc = "Reader of field `EMPTY`"]
172pub type EMPTY_R = crate::R<bool, bool>;
173#[doc = "Write proxy for field `EMPTY`"]
174pub struct EMPTY_W<'a> {
175 w: &'a mut W,
176}
177impl<'a> EMPTY_W<'a> {
178 #[doc = r"Sets the field bit"]
179 #[inline(always)]
180 pub fn set_bit(self) -> &'a mut W {
181 self.bit(true)
182 }
183 #[doc = r"Clears the field bit"]
184 #[inline(always)]
185 pub fn clear_bit(self) -> &'a mut W {
186 self.bit(false)
187 }
188 #[doc = r"Writes raw bits to the field"]
189 #[inline(always)]
190 pub fn bit(self, value: bool) -> &'a mut W {
191 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
192 self.w
193 }
194}
195impl R {
196 #[doc = "Bits 0:2 - Latency"]
197 #[inline(always)]
198 pub fn latency(&self) -> LATENCY_R {
199 LATENCY_R::new((self.bits & 0x07) as u8)
200 }
201 #[doc = "Bit 8 - Prefetch enable"]
202 #[inline(always)]
203 pub fn prften(&self) -> PRFTEN_R {
204 PRFTEN_R::new(((self.bits >> 8) & 0x01) != 0)
205 }
206 #[doc = "Bit 9 - Instruction cache enable"]
207 #[inline(always)]
208 pub fn icen(&self) -> ICEN_R {
209 ICEN_R::new(((self.bits >> 9) & 0x01) != 0)
210 }
211 #[doc = "Bit 10 - Data cache enable"]
212 #[inline(always)]
213 pub fn dcen(&self) -> DCEN_R {
214 DCEN_R::new(((self.bits >> 10) & 0x01) != 0)
215 }
216 #[doc = "Bit 11 - Instruction cache reset"]
217 #[inline(always)]
218 pub fn icrst(&self) -> ICRST_R {
219 ICRST_R::new(((self.bits >> 11) & 0x01) != 0)
220 }
221 #[doc = "Bit 12 - Data cache reset"]
222 #[inline(always)]
223 pub fn dcrst(&self) -> DCRST_R {
224 DCRST_R::new(((self.bits >> 12) & 0x01) != 0)
225 }
226 #[doc = "Bit 15 - CPU1 CortexM4 program erase suspend request"]
227 #[inline(always)]
228 pub fn pes(&self) -> PES_R {
229 PES_R::new(((self.bits >> 15) & 0x01) != 0)
230 }
231 #[doc = "Bit 16 - Flash User area empty"]
232 #[inline(always)]
233 pub fn empty(&self) -> EMPTY_R {
234 EMPTY_R::new(((self.bits >> 16) & 0x01) != 0)
235 }
236}
237impl W {
238 #[doc = "Bits 0:2 - Latency"]
239 #[inline(always)]
240 pub fn latency(&mut self) -> LATENCY_W {
241 LATENCY_W { w: self }
242 }
243 #[doc = "Bit 8 - Prefetch enable"]
244 #[inline(always)]
245 pub fn prften(&mut self) -> PRFTEN_W {
246 PRFTEN_W { w: self }
247 }
248 #[doc = "Bit 9 - Instruction cache enable"]
249 #[inline(always)]
250 pub fn icen(&mut self) -> ICEN_W {
251 ICEN_W { w: self }
252 }
253 #[doc = "Bit 10 - Data cache enable"]
254 #[inline(always)]
255 pub fn dcen(&mut self) -> DCEN_W {
256 DCEN_W { w: self }
257 }
258 #[doc = "Bit 11 - Instruction cache reset"]
259 #[inline(always)]
260 pub fn icrst(&mut self) -> ICRST_W {
261 ICRST_W { w: self }
262 }
263 #[doc = "Bit 12 - Data cache reset"]
264 #[inline(always)]
265 pub fn dcrst(&mut self) -> DCRST_W {
266 DCRST_W { w: self }
267 }
268 #[doc = "Bit 15 - CPU1 CortexM4 program erase suspend request"]
269 #[inline(always)]
270 pub fn pes(&mut self) -> PES_W {
271 PES_W { w: self }
272 }
273 #[doc = "Bit 16 - Flash User area empty"]
274 #[inline(always)]
275 pub fn empty(&mut self) -> EMPTY_W {
276 EMPTY_W { w: self }
277 }
278}