stm32wb_pac/exti/
c1imr2.rs

1#[doc = "Reader of register C1IMR2"]
2pub type R = crate::R<u32, super::C1IMR2>;
3#[doc = "Writer for register C1IMR2"]
4pub type W = crate::W<u32, super::C1IMR2>;
5#[doc = "Register C1IMR2 `reset()`'s with value 0x0001_fcfd"]
6impl crate::ResetValue for super::C1IMR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x0001_fcfd
11    }
12}
13#[doc = "Reader of field `IM`"]
14pub type IM_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `IM`"]
16pub struct IM_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> IM_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x0001_ffff) | ((value as u32) & 0x0001_ffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input"]
29    #[inline(always)]
30    pub fn im(&self) -> IM_R {
31        IM_R::new((self.bits & 0x0001_ffff) as u32)
32    }
33}
34impl W {
35    #[doc = "Bits 0:16 - CPUm Wakeup with interrupt Mask on Event input"]
36    #[inline(always)]
37    pub fn im(&mut self) -> IM_W {
38        IM_W { w: self }
39    }
40}
stm32wb_pac/exti/c1imr2.rs

stm32wb_pac/exti/
c1imr2.rs
