stm32wb_pac/dmamux1/
rg3cr.rs

1#[doc = "Reader of register RG3CR"]
2pub type R = crate::R<u32, super::RG3CR>;
3#[doc = "Writer for register RG3CR"]
4pub type W = crate::W<u32, super::RG3CR>;
5#[doc = "Register RG3CR `reset()`'s with value 0"]
6impl crate::ResetValue for super::RG3CR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `GNBREQ`"]
14pub type GNBREQ_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `GNBREQ`"]
16pub struct GNBREQ_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> GNBREQ_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
24        self.w
25    }
26}
27#[doc = "Reader of field `GPOL`"]
28pub type GPOL_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `GPOL`"]
30pub struct GPOL_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> GPOL_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
38        self.w
39    }
40}
41#[doc = "Reader of field `GE`"]
42pub type GE_R = crate::R<bool, bool>;
43#[doc = "Write proxy for field `GE`"]
44pub struct GE_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> GE_W<'a> {
48    #[doc = r"Sets the field bit"]
49    #[inline(always)]
50    pub fn set_bit(self) -> &'a mut W {
51        self.bit(true)
52    }
53    #[doc = r"Clears the field bit"]
54    #[inline(always)]
55    pub fn clear_bit(self) -> &'a mut W {
56        self.bit(false)
57    }
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub fn bit(self, value: bool) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
62        self.w
63    }
64}
65#[doc = "Reader of field `OIE`"]
66pub type OIE_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `OIE`"]
68pub struct OIE_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> OIE_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
86        self.w
87    }
88}
89#[doc = "Reader of field `SIG_ID`"]
90pub type SIG_ID_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `SIG_ID`"]
92pub struct SIG_ID_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> SIG_ID_W<'a> {
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub unsafe fn bits(self, value: u8) -> &'a mut W {
99        self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
100        self.w
101    }
102}
103impl R {
104    #[doc = "Bits 19:23 - Number of Request"]
105    #[inline(always)]
106    pub fn gnbreq(&self) -> GNBREQ_R {
107        GNBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
108    }
109    #[doc = "Bits 17:18 - Generation Polarity"]
110    #[inline(always)]
111    pub fn gpol(&self) -> GPOL_R {
112        GPOL_R::new(((self.bits >> 17) & 0x03) as u8)
113    }
114    #[doc = "Bit 16 - Generation Enable"]
115    #[inline(always)]
116    pub fn ge(&self) -> GE_R {
117        GE_R::new(((self.bits >> 16) & 0x01) != 0)
118    }
119    #[doc = "Bit 8 - Overrun Interrupt Enable"]
120    #[inline(always)]
121    pub fn oie(&self) -> OIE_R {
122        OIE_R::new(((self.bits >> 8) & 0x01) != 0)
123    }
124    #[doc = "Bits 0:4 - Signal ID"]
125    #[inline(always)]
126    pub fn sig_id(&self) -> SIG_ID_R {
127        SIG_ID_R::new((self.bits & 0x1f) as u8)
128    }
129}
130impl W {
131    #[doc = "Bits 19:23 - Number of Request"]
132    #[inline(always)]
133    pub fn gnbreq(&mut self) -> GNBREQ_W {
134        GNBREQ_W { w: self }
135    }
136    #[doc = "Bits 17:18 - Generation Polarity"]
137    #[inline(always)]
138    pub fn gpol(&mut self) -> GPOL_W {
139        GPOL_W { w: self }
140    }
141    #[doc = "Bit 16 - Generation Enable"]
142    #[inline(always)]
143    pub fn ge(&mut self) -> GE_W {
144        GE_W { w: self }
145    }
146    #[doc = "Bit 8 - Overrun Interrupt Enable"]
147    #[inline(always)]
148    pub fn oie(&mut self) -> OIE_W {
149        OIE_W { w: self }
150    }
151    #[doc = "Bits 0:4 - Signal ID"]
152    #[inline(always)]
153    pub fn sig_id(&mut self) -> SIG_ID_W {
154        SIG_ID_W { w: self }
155    }
156}
stm32wb_pac/dmamux1/rg3cr.rs

stm32wb_pac/dmamux1/
rg3cr.rs
