stm32wb_pac/dmamux1/
c3cr.rs1#[doc = "Reader of register C3CR"]
2pub type R = crate::R<u32, super::C3CR>;
3#[doc = "Writer for register C3CR"]
4pub type W = crate::W<u32, super::C3CR>;
5#[doc = "Register C3CR `reset()`'s with value 0"]
6impl crate::ResetValue for super::C3CR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `SYNC_ID`"]
14pub type SYNC_ID_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `SYNC_ID`"]
16pub struct SYNC_ID_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> SYNC_ID_W<'a> {
20 #[doc = r"Writes raw bits to the field"]
21 #[inline(always)]
22 pub unsafe fn bits(self, value: u8) -> &'a mut W {
23 self.w.bits = (self.w.bits & !(0x1f << 24)) | (((value as u32) & 0x1f) << 24);
24 self.w
25 }
26}
27#[doc = "Reader of field `NBREQ`"]
28pub type NBREQ_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `NBREQ`"]
30pub struct NBREQ_W<'a> {
31 w: &'a mut W,
32}
33impl<'a> NBREQ_W<'a> {
34 #[doc = r"Writes raw bits to the field"]
35 #[inline(always)]
36 pub unsafe fn bits(self, value: u8) -> &'a mut W {
37 self.w.bits = (self.w.bits & !(0x1f << 19)) | (((value as u32) & 0x1f) << 19);
38 self.w
39 }
40}
41#[doc = "Reader of field `SPOL`"]
42pub type SPOL_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `SPOL`"]
44pub struct SPOL_W<'a> {
45 w: &'a mut W,
46}
47impl<'a> SPOL_W<'a> {
48 #[doc = r"Writes raw bits to the field"]
49 #[inline(always)]
50 pub unsafe fn bits(self, value: u8) -> &'a mut W {
51 self.w.bits = (self.w.bits & !(0x03 << 17)) | (((value as u32) & 0x03) << 17);
52 self.w
53 }
54}
55#[doc = "Reader of field `SE`"]
56pub type SE_R = crate::R<bool, bool>;
57#[doc = "Write proxy for field `SE`"]
58pub struct SE_W<'a> {
59 w: &'a mut W,
60}
61impl<'a> SE_W<'a> {
62 #[doc = r"Sets the field bit"]
63 #[inline(always)]
64 pub fn set_bit(self) -> &'a mut W {
65 self.bit(true)
66 }
67 #[doc = r"Clears the field bit"]
68 #[inline(always)]
69 pub fn clear_bit(self) -> &'a mut W {
70 self.bit(false)
71 }
72 #[doc = r"Writes raw bits to the field"]
73 #[inline(always)]
74 pub fn bit(self, value: bool) -> &'a mut W {
75 self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
76 self.w
77 }
78}
79#[doc = "Reader of field `EGE`"]
80pub type EGE_R = crate::R<bool, bool>;
81#[doc = "Write proxy for field `EGE`"]
82pub struct EGE_W<'a> {
83 w: &'a mut W,
84}
85impl<'a> EGE_W<'a> {
86 #[doc = r"Sets the field bit"]
87 #[inline(always)]
88 pub fn set_bit(self) -> &'a mut W {
89 self.bit(true)
90 }
91 #[doc = r"Clears the field bit"]
92 #[inline(always)]
93 pub fn clear_bit(self) -> &'a mut W {
94 self.bit(false)
95 }
96 #[doc = r"Writes raw bits to the field"]
97 #[inline(always)]
98 pub fn bit(self, value: bool) -> &'a mut W {
99 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
100 self.w
101 }
102}
103#[doc = "Reader of field `SOIE`"]
104pub type SOIE_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `SOIE`"]
106pub struct SOIE_W<'a> {
107 w: &'a mut W,
108}
109impl<'a> SOIE_W<'a> {
110 #[doc = r"Sets the field bit"]
111 #[inline(always)]
112 pub fn set_bit(self) -> &'a mut W {
113 self.bit(true)
114 }
115 #[doc = r"Clears the field bit"]
116 #[inline(always)]
117 pub fn clear_bit(self) -> &'a mut W {
118 self.bit(false)
119 }
120 #[doc = r"Writes raw bits to the field"]
121 #[inline(always)]
122 pub fn bit(self, value: bool) -> &'a mut W {
123 self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
124 self.w
125 }
126}
127#[doc = "Reader of field `DMAREQ_ID`"]
128pub type DMAREQ_ID_R = crate::R<u8, u8>;
129#[doc = "Write proxy for field `DMAREQ_ID`"]
130pub struct DMAREQ_ID_W<'a> {
131 w: &'a mut W,
132}
133impl<'a> DMAREQ_ID_W<'a> {
134 #[doc = r"Writes raw bits to the field"]
135 #[inline(always)]
136 pub unsafe fn bits(self, value: u8) -> &'a mut W {
137 self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
138 self.w
139 }
140}
141impl R {
142 #[doc = "Bits 24:28 - SYNC_ID"]
143 #[inline(always)]
144 pub fn sync_id(&self) -> SYNC_ID_R {
145 SYNC_ID_R::new(((self.bits >> 24) & 0x1f) as u8)
146 }
147 #[doc = "Bits 19:23 - Nb request"]
148 #[inline(always)]
149 pub fn nbreq(&self) -> NBREQ_R {
150 NBREQ_R::new(((self.bits >> 19) & 0x1f) as u8)
151 }
152 #[doc = "Bits 17:18 - Sync polarity"]
153 #[inline(always)]
154 pub fn spol(&self) -> SPOL_R {
155 SPOL_R::new(((self.bits >> 17) & 0x03) as u8)
156 }
157 #[doc = "Bit 16 - Synchronization enable"]
158 #[inline(always)]
159 pub fn se(&self) -> SE_R {
160 SE_R::new(((self.bits >> 16) & 0x01) != 0)
161 }
162 #[doc = "Bit 9 - Event Generation Enable"]
163 #[inline(always)]
164 pub fn ege(&self) -> EGE_R {
165 EGE_R::new(((self.bits >> 9) & 0x01) != 0)
166 }
167 #[doc = "Bit 8 - Synchronization Overrun Interrupt Enable"]
168 #[inline(always)]
169 pub fn soie(&self) -> SOIE_R {
170 SOIE_R::new(((self.bits >> 8) & 0x01) != 0)
171 }
172 #[doc = "Bits 0:7 - DMA Request ID"]
173 #[inline(always)]
174 pub fn dmareq_id(&self) -> DMAREQ_ID_R {
175 DMAREQ_ID_R::new((self.bits & 0xff) as u8)
176 }
177}
178impl W {
179 #[doc = "Bits 24:28 - SYNC_ID"]
180 #[inline(always)]
181 pub fn sync_id(&mut self) -> SYNC_ID_W {
182 SYNC_ID_W { w: self }
183 }
184 #[doc = "Bits 19:23 - Nb request"]
185 #[inline(always)]
186 pub fn nbreq(&mut self) -> NBREQ_W {
187 NBREQ_W { w: self }
188 }
189 #[doc = "Bits 17:18 - Sync polarity"]
190 #[inline(always)]
191 pub fn spol(&mut self) -> SPOL_W {
192 SPOL_W { w: self }
193 }
194 #[doc = "Bit 16 - Synchronization enable"]
195 #[inline(always)]
196 pub fn se(&mut self) -> SE_W {
197 SE_W { w: self }
198 }
199 #[doc = "Bit 9 - Event Generation Enable"]
200 #[inline(always)]
201 pub fn ege(&mut self) -> EGE_W {
202 EGE_W { w: self }
203 }
204 #[doc = "Bit 8 - Synchronization Overrun Interrupt Enable"]
205 #[inline(always)]
206 pub fn soie(&mut self) -> SOIE_W {
207 SOIE_W { w: self }
208 }
209 #[doc = "Bits 0:7 - DMA Request ID"]
210 #[inline(always)]
211 pub fn dmareq_id(&mut self) -> DMAREQ_ID_W {
212 DMAREQ_ID_W { w: self }
213 }
214}