stm32wb_pac/dma2/
cselr.rs

1#[doc = "Reader of register CSELR"]
2pub type R = crate::R<u32, super::CSELR>;
3#[doc = "Writer for register CSELR"]
4pub type W = crate::W<u32, super::CSELR>;
5#[doc = "Register CSELR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CSELR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `C7S`"]
14pub type C7S_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `C7S`"]
16pub struct C7S_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> C7S_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x0f << 24)) | (((value as u32) & 0x0f) << 24);
24        self.w
25    }
26}
27#[doc = "Reader of field `C6S`"]
28pub type C6S_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `C6S`"]
30pub struct C6S_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> C6S_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x0f << 20)) | (((value as u32) & 0x0f) << 20);
38        self.w
39    }
40}
41#[doc = "Reader of field `C5S`"]
42pub type C5S_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `C5S`"]
44pub struct C5S_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> C5S_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
52        self.w
53    }
54}
55#[doc = "Reader of field `C4S`"]
56pub type C4S_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `C4S`"]
58pub struct C4S_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> C4S_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !(0x0f << 12)) | (((value as u32) & 0x0f) << 12);
66        self.w
67    }
68}
69#[doc = "Reader of field `C3S`"]
70pub type C3S_R = crate::R<u8, u8>;
71#[doc = "Write proxy for field `C3S`"]
72pub struct C3S_W<'a> {
73    w: &'a mut W,
74}
75impl<'a> C3S_W<'a> {
76    #[doc = r"Writes raw bits to the field"]
77    #[inline(always)]
78    pub unsafe fn bits(self, value: u8) -> &'a mut W {
79        self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u32) & 0x0f) << 8);
80        self.w
81    }
82}
83#[doc = "Reader of field `C2S`"]
84pub type C2S_R = crate::R<u8, u8>;
85#[doc = "Write proxy for field `C2S`"]
86pub struct C2S_W<'a> {
87    w: &'a mut W,
88}
89impl<'a> C2S_W<'a> {
90    #[doc = r"Writes raw bits to the field"]
91    #[inline(always)]
92    pub unsafe fn bits(self, value: u8) -> &'a mut W {
93        self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4);
94        self.w
95    }
96}
97#[doc = "Reader of field `C1S`"]
98pub type C1S_R = crate::R<u8, u8>;
99#[doc = "Write proxy for field `C1S`"]
100pub struct C1S_W<'a> {
101    w: &'a mut W,
102}
103impl<'a> C1S_W<'a> {
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub unsafe fn bits(self, value: u8) -> &'a mut W {
107        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
108        self.w
109    }
110}
111impl R {
112    #[doc = "Bits 24:27 - DMA channel 7 selection"]
113    #[inline(always)]
114    pub fn c7s(&self) -> C7S_R {
115        C7S_R::new(((self.bits >> 24) & 0x0f) as u8)
116    }
117    #[doc = "Bits 20:23 - DMA channel 6 selection"]
118    #[inline(always)]
119    pub fn c6s(&self) -> C6S_R {
120        C6S_R::new(((self.bits >> 20) & 0x0f) as u8)
121    }
122    #[doc = "Bits 16:19 - DMA channel 5 selection"]
123    #[inline(always)]
124    pub fn c5s(&self) -> C5S_R {
125        C5S_R::new(((self.bits >> 16) & 0x0f) as u8)
126    }
127    #[doc = "Bits 12:15 - DMA channel 4 selection"]
128    #[inline(always)]
129    pub fn c4s(&self) -> C4S_R {
130        C4S_R::new(((self.bits >> 12) & 0x0f) as u8)
131    }
132    #[doc = "Bits 8:11 - DMA channel 3 selection"]
133    #[inline(always)]
134    pub fn c3s(&self) -> C3S_R {
135        C3S_R::new(((self.bits >> 8) & 0x0f) as u8)
136    }
137    #[doc = "Bits 4:7 - DMA channel 2 selection"]
138    #[inline(always)]
139    pub fn c2s(&self) -> C2S_R {
140        C2S_R::new(((self.bits >> 4) & 0x0f) as u8)
141    }
142    #[doc = "Bits 0:3 - DMA channel 1 selection"]
143    #[inline(always)]
144    pub fn c1s(&self) -> C1S_R {
145        C1S_R::new((self.bits & 0x0f) as u8)
146    }
147}
148impl W {
149    #[doc = "Bits 24:27 - DMA channel 7 selection"]
150    #[inline(always)]
151    pub fn c7s(&mut self) -> C7S_W {
152        C7S_W { w: self }
153    }
154    #[doc = "Bits 20:23 - DMA channel 6 selection"]
155    #[inline(always)]
156    pub fn c6s(&mut self) -> C6S_W {
157        C6S_W { w: self }
158    }
159    #[doc = "Bits 16:19 - DMA channel 5 selection"]
160    #[inline(always)]
161    pub fn c5s(&mut self) -> C5S_W {
162        C5S_W { w: self }
163    }
164    #[doc = "Bits 12:15 - DMA channel 4 selection"]
165    #[inline(always)]
166    pub fn c4s(&mut self) -> C4S_W {
167        C4S_W { w: self }
168    }
169    #[doc = "Bits 8:11 - DMA channel 3 selection"]
170    #[inline(always)]
171    pub fn c3s(&mut self) -> C3S_W {
172        C3S_W { w: self }
173    }
174    #[doc = "Bits 4:7 - DMA channel 2 selection"]
175    #[inline(always)]
176    pub fn c2s(&mut self) -> C2S_W {
177        C2S_W { w: self }
178    }
179    #[doc = "Bits 0:3 - DMA channel 1 selection"]
180    #[inline(always)]
181    pub fn c1s(&mut self) -> C1S_W {
182        C1S_W { w: self }
183    }
184}
stm32wb_pac/dma2/cselr.rs

stm32wb_pac/dma2/
cselr.rs
