stm32wb_pac/dbgmcu/
c2apb1fzr2.rs

1#[doc = "Reader of register C2APB1FZR2"]
2pub type R = crate::R<u32, super::C2APB1FZR2>;
3#[doc = "Writer for register C2APB1FZR2"]
4pub type W = crate::W<u32, super::C2APB1FZR2>;
5#[doc = "Register C2APB1FZR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::C2APB1FZR2 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DBG_LPTIM2_STOP`"]
14pub type DBG_LPTIM2_STOP_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DBG_LPTIM2_STOP`"]
16pub struct DBG_LPTIM2_STOP_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DBG_LPTIM2_STOP_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
34        self.w
35    }
36}
37impl R {
38    #[doc = "Bit 5 - LPTIM2 counter stopped when core is halted"]
39    #[inline(always)]
40    pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R {
41        DBG_LPTIM2_STOP_R::new(((self.bits >> 5) & 0x01) != 0)
42    }
43}
44impl W {
45    #[doc = "Bit 5 - LPTIM2 counter stopped when core is halted"]
46    #[inline(always)]
47    pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W {
48        DBG_LPTIM2_STOP_W { w: self }
49    }
50}
stm32wb_pac/dbgmcu/c2apb1fzr2.rs

stm32wb_pac/dbgmcu/
c2apb1fzr2.rs
