stm32wb_pac/dbgmcu/
apb1fzr1.rs

1#[doc = "Reader of register APB1FZR1"]
2pub type R = crate::R<u32, super::APB1FZR1>;
3#[doc = "Writer for register APB1FZR1"]
4pub type W = crate::W<u32, super::APB1FZR1>;
5#[doc = "Register APB1FZR1 `reset()`'s with value 0"]
6impl crate::ResetValue for super::APB1FZR1 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DBG_TIMER2_STOP`"]
14pub type DBG_TIMER2_STOP_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DBG_TIMER2_STOP`"]
16pub struct DBG_TIMER2_STOP_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DBG_TIMER2_STOP_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `DBG_RTC_STOP`"]
38pub type DBG_RTC_STOP_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `DBG_RTC_STOP`"]
40pub struct DBG_RTC_STOP_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> DBG_RTC_STOP_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
58        self.w
59    }
60}
61#[doc = "Reader of field `DBG_WWDG_STOP`"]
62pub type DBG_WWDG_STOP_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `DBG_WWDG_STOP`"]
64pub struct DBG_WWDG_STOP_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> DBG_WWDG_STOP_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
82        self.w
83    }
84}
85#[doc = "Reader of field `DBG_IWDG_STOP`"]
86pub type DBG_IWDG_STOP_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DBG_IWDG_STOP`"]
88pub struct DBG_IWDG_STOP_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DBG_IWDG_STOP_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
106        self.w
107    }
108}
109#[doc = "Reader of field `DBG_I2C1_STOP`"]
110pub type DBG_I2C1_STOP_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `DBG_I2C1_STOP`"]
112pub struct DBG_I2C1_STOP_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> DBG_I2C1_STOP_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
130        self.w
131    }
132}
133#[doc = "Reader of field `DBG_I2C3_STOP`"]
134pub type DBG_I2C3_STOP_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `DBG_I2C3_STOP`"]
136pub struct DBG_I2C3_STOP_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> DBG_I2C3_STOP_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23);
154        self.w
155    }
156}
157#[doc = "Reader of field `DBG_LPTIM1_STOP`"]
158pub type DBG_LPTIM1_STOP_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `DBG_LPTIM1_STOP`"]
160pub struct DBG_LPTIM1_STOP_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DBG_LPTIM1_STOP_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
178        self.w
179    }
180}
181impl R {
182    #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
183    #[inline(always)]
184    pub fn dbg_timer2_stop(&self) -> DBG_TIMER2_STOP_R {
185        DBG_TIMER2_STOP_R::new((self.bits & 0x01) != 0)
186    }
187    #[doc = "Bit 10 - RTC counter stopped when core is halted"]
188    #[inline(always)]
189    pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R {
190        DBG_RTC_STOP_R::new(((self.bits >> 10) & 0x01) != 0)
191    }
192    #[doc = "Bit 11 - WWDG counter stopped when core is halted"]
193    #[inline(always)]
194    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
195        DBG_WWDG_STOP_R::new(((self.bits >> 11) & 0x01) != 0)
196    }
197    #[doc = "Bit 12 - IWDG counter stopped when core is halted"]
198    #[inline(always)]
199    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
200        DBG_IWDG_STOP_R::new(((self.bits >> 12) & 0x01) != 0)
201    }
202    #[doc = "Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted"]
203    #[inline(always)]
204    pub fn dbg_i2c1_stop(&self) -> DBG_I2C1_STOP_R {
205        DBG_I2C1_STOP_R::new(((self.bits >> 21) & 0x01) != 0)
206    }
207    #[doc = "Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted"]
208    #[inline(always)]
209    pub fn dbg_i2c3_stop(&self) -> DBG_I2C3_STOP_R {
210        DBG_I2C3_STOP_R::new(((self.bits >> 23) & 0x01) != 0)
211    }
212    #[doc = "Bit 31 - Debug LPTIM1 stopped when Core is halted"]
213    #[inline(always)]
214    pub fn dbg_lptim1_stop(&self) -> DBG_LPTIM1_STOP_R {
215        DBG_LPTIM1_STOP_R::new(((self.bits >> 31) & 0x01) != 0)
216    }
217}
218impl W {
219    #[doc = "Bit 0 - Debug Timer 2 stopped when Core is halted"]
220    #[inline(always)]
221    pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W {
222        DBG_TIMER2_STOP_W { w: self }
223    }
224    #[doc = "Bit 10 - RTC counter stopped when core is halted"]
225    #[inline(always)]
226    pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W {
227        DBG_RTC_STOP_W { w: self }
228    }
229    #[doc = "Bit 11 - WWDG counter stopped when core is halted"]
230    #[inline(always)]
231    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W {
232        DBG_WWDG_STOP_W { w: self }
233    }
234    #[doc = "Bit 12 - IWDG counter stopped when core is halted"]
235    #[inline(always)]
236    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W {
237        DBG_IWDG_STOP_W { w: self }
238    }
239    #[doc = "Bit 21 - Debug I2C1 SMBUS timeout stopped when Core is halted"]
240    #[inline(always)]
241    pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W {
242        DBG_I2C1_STOP_W { w: self }
243    }
244    #[doc = "Bit 23 - Debug I2C3 SMBUS timeout stopped when core is halted"]
245    #[inline(always)]
246    pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W {
247        DBG_I2C3_STOP_W { w: self }
248    }
249    #[doc = "Bit 31 - Debug LPTIM1 stopped when Core is halted"]
250    #[inline(always)]
251    pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W {
252        DBG_LPTIM1_STOP_W { w: self }
253    }
254}
stm32wb_pac/dbgmcu/apb1fzr1.rs

stm32wb_pac/dbgmcu/
apb1fzr1.rs
