stm32wb_pac/crs/
cfgr.rs

1#[doc = "Reader of register CFGR"]
2pub type R = crate::R<u32, super::CFGR>;
3#[doc = "Writer for register CFGR"]
4pub type W = crate::W<u32, super::CFGR>;
5#[doc = "Register CFGR `reset()`'s with value 0x2022_bb7f"]
6impl crate::ResetValue for super::CFGR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x2022_bb7f
11    }
12}
13#[doc = "Reader of field `RELOAD`"]
14pub type RELOAD_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `RELOAD`"]
16pub struct RELOAD_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> RELOAD_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
24        self.w
25    }
26}
27#[doc = "Reader of field `FELIM`"]
28pub type FELIM_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `FELIM`"]
30pub struct FELIM_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> FELIM_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
38        self.w
39    }
40}
41#[doc = "Reader of field `SYNCDIV`"]
42pub type SYNCDIV_R = crate::R<u8, u8>;
43#[doc = "Write proxy for field `SYNCDIV`"]
44pub struct SYNCDIV_W<'a> {
45    w: &'a mut W,
46}
47impl<'a> SYNCDIV_W<'a> {
48    #[doc = r"Writes raw bits to the field"]
49    #[inline(always)]
50    pub unsafe fn bits(self, value: u8) -> &'a mut W {
51        self.w.bits = (self.w.bits & !(0x07 << 24)) | (((value as u32) & 0x07) << 24);
52        self.w
53    }
54}
55#[doc = "Reader of field `SYNCSRC`"]
56pub type SYNCSRC_R = crate::R<u8, u8>;
57#[doc = "Write proxy for field `SYNCSRC`"]
58pub struct SYNCSRC_W<'a> {
59    w: &'a mut W,
60}
61impl<'a> SYNCSRC_W<'a> {
62    #[doc = r"Writes raw bits to the field"]
63    #[inline(always)]
64    pub unsafe fn bits(self, value: u8) -> &'a mut W {
65        self.w.bits = (self.w.bits & !(0x03 << 28)) | (((value as u32) & 0x03) << 28);
66        self.w
67    }
68}
69#[doc = "Reader of field `SYNCPOL`"]
70pub type SYNCPOL_R = crate::R<bool, bool>;
71#[doc = "Write proxy for field `SYNCPOL`"]
72pub struct SYNCPOL_W<'a> {
73    w: &'a mut W,
74}
75impl<'a> SYNCPOL_W<'a> {
76    #[doc = r"Sets the field bit"]
77    #[inline(always)]
78    pub fn set_bit(self) -> &'a mut W {
79        self.bit(true)
80    }
81    #[doc = r"Clears the field bit"]
82    #[inline(always)]
83    pub fn clear_bit(self) -> &'a mut W {
84        self.bit(false)
85    }
86    #[doc = r"Writes raw bits to the field"]
87    #[inline(always)]
88    pub fn bit(self, value: bool) -> &'a mut W {
89        self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
90        self.w
91    }
92}
93impl R {
94    #[doc = "Bits 0:15 - Counter reload value"]
95    #[inline(always)]
96    pub fn reload(&self) -> RELOAD_R {
97        RELOAD_R::new((self.bits & 0xffff) as u16)
98    }
99    #[doc = "Bits 16:23 - Frequency error limit"]
100    #[inline(always)]
101    pub fn felim(&self) -> FELIM_R {
102        FELIM_R::new(((self.bits >> 16) & 0xff) as u8)
103    }
104    #[doc = "Bits 24:26 - SYNCDIV"]
105    #[inline(always)]
106    pub fn syncdiv(&self) -> SYNCDIV_R {
107        SYNCDIV_R::new(((self.bits >> 24) & 0x07) as u8)
108    }
109    #[doc = "Bits 28:29 - SYNC signal source selection"]
110    #[inline(always)]
111    pub fn syncsrc(&self) -> SYNCSRC_R {
112        SYNCSRC_R::new(((self.bits >> 28) & 0x03) as u8)
113    }
114    #[doc = "Bit 31 - SYNC polarity selection"]
115    #[inline(always)]
116    pub fn syncpol(&self) -> SYNCPOL_R {
117        SYNCPOL_R::new(((self.bits >> 31) & 0x01) != 0)
118    }
119}
120impl W {
121    #[doc = "Bits 0:15 - Counter reload value"]
122    #[inline(always)]
123    pub fn reload(&mut self) -> RELOAD_W {
124        RELOAD_W { w: self }
125    }
126    #[doc = "Bits 16:23 - Frequency error limit"]
127    #[inline(always)]
128    pub fn felim(&mut self) -> FELIM_W {
129        FELIM_W { w: self }
130    }
131    #[doc = "Bits 24:26 - SYNCDIV"]
132    #[inline(always)]
133    pub fn syncdiv(&mut self) -> SYNCDIV_W {
134        SYNCDIV_W { w: self }
135    }
136    #[doc = "Bits 28:29 - SYNC signal source selection"]
137    #[inline(always)]
138    pub fn syncsrc(&mut self) -> SYNCSRC_W {
139        SYNCSRC_W { w: self }
140    }
141    #[doc = "Bit 31 - SYNC polarity selection"]
142    #[inline(always)]
143    pub fn syncpol(&mut self) -> SYNCPOL_W {
144        SYNCPOL_W { w: self }
145    }
146}
stm32wb_pac/crs/cfgr.rs

stm32wb_pac/crs/
cfgr.rs
