1#[doc = "Reader of register CFGR2"]
2pub type R = crate::R<u32, super::CFGR2>;
3#[doc = "Writer for register CFGR2"]
4pub type W = crate::W<u32, super::CFGR2>;
5#[doc = "Register CFGR2 `reset()`'s with value 0"]
6impl crate::ResetValue for super::CFGR2 {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `ROVSM`"]
14pub type ROVSM_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `ROVSM`"]
16pub struct ROVSM_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> ROVSM_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
34 self.w
35 }
36}
37#[doc = "Reader of field `TOVS`"]
38pub type TOVS_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `TOVS`"]
40pub struct TOVS_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> TOVS_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
58 self.w
59 }
60}
61#[doc = "Reader of field `OVSS`"]
62pub type OVSS_R = crate::R<u8, u8>;
63#[doc = "Write proxy for field `OVSS`"]
64pub struct OVSS_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> OVSS_W<'a> {
68 #[doc = r"Writes raw bits to the field"]
69 #[inline(always)]
70 pub unsafe fn bits(self, value: u8) -> &'a mut W {
71 self.w.bits = (self.w.bits & !(0x0f << 5)) | (((value as u32) & 0x0f) << 5);
72 self.w
73 }
74}
75#[doc = "Reader of field `OVSR`"]
76pub type OVSR_R = crate::R<u8, u8>;
77#[doc = "Write proxy for field `OVSR`"]
78pub struct OVSR_W<'a> {
79 w: &'a mut W,
80}
81impl<'a> OVSR_W<'a> {
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub unsafe fn bits(self, value: u8) -> &'a mut W {
85 self.w.bits = (self.w.bits & !(0x07 << 2)) | (((value as u32) & 0x07) << 2);
86 self.w
87 }
88}
89#[doc = "Reader of field `JOVSE`"]
90pub type JOVSE_R = crate::R<bool, bool>;
91#[doc = "Write proxy for field `JOVSE`"]
92pub struct JOVSE_W<'a> {
93 w: &'a mut W,
94}
95impl<'a> JOVSE_W<'a> {
96 #[doc = r"Sets the field bit"]
97 #[inline(always)]
98 pub fn set_bit(self) -> &'a mut W {
99 self.bit(true)
100 }
101 #[doc = r"Clears the field bit"]
102 #[inline(always)]
103 pub fn clear_bit(self) -> &'a mut W {
104 self.bit(false)
105 }
106 #[doc = r"Writes raw bits to the field"]
107 #[inline(always)]
108 pub fn bit(self, value: bool) -> &'a mut W {
109 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
110 self.w
111 }
112}
113#[doc = "Reader of field `ROVSE`"]
114pub type ROVSE_R = crate::R<bool, bool>;
115#[doc = "Write proxy for field `ROVSE`"]
116pub struct ROVSE_W<'a> {
117 w: &'a mut W,
118}
119impl<'a> ROVSE_W<'a> {
120 #[doc = r"Sets the field bit"]
121 #[inline(always)]
122 pub fn set_bit(self) -> &'a mut W {
123 self.bit(true)
124 }
125 #[doc = r"Clears the field bit"]
126 #[inline(always)]
127 pub fn clear_bit(self) -> &'a mut W {
128 self.bit(false)
129 }
130 #[doc = r"Writes raw bits to the field"]
131 #[inline(always)]
132 pub fn bit(self, value: bool) -> &'a mut W {
133 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
134 self.w
135 }
136}
137impl R {
138 #[doc = "Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected"]
139 #[inline(always)]
140 pub fn rovsm(&self) -> ROVSM_R {
141 ROVSM_R::new(((self.bits >> 10) & 0x01) != 0)
142 }
143 #[doc = "Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular"]
144 #[inline(always)]
145 pub fn tovs(&self) -> TOVS_R {
146 TOVS_R::new(((self.bits >> 9) & 0x01) != 0)
147 }
148 #[doc = "Bits 5:8 - ADC oversampling shift"]
149 #[inline(always)]
150 pub fn ovss(&self) -> OVSS_R {
151 OVSS_R::new(((self.bits >> 5) & 0x0f) as u8)
152 }
153 #[doc = "Bits 2:4 - ADC oversampling ratio"]
154 #[inline(always)]
155 pub fn ovsr(&self) -> OVSR_R {
156 OVSR_R::new(((self.bits >> 2) & 0x07) as u8)
157 }
158 #[doc = "Bit 1 - ADC oversampler enable on scope ADC group injected"]
159 #[inline(always)]
160 pub fn jovse(&self) -> JOVSE_R {
161 JOVSE_R::new(((self.bits >> 1) & 0x01) != 0)
162 }
163 #[doc = "Bit 0 - ADC oversampler enable on scope ADC group regular"]
164 #[inline(always)]
165 pub fn rovse(&self) -> ROVSE_R {
166 ROVSE_R::new((self.bits & 0x01) != 0)
167 }
168}
169impl W {
170 #[doc = "Bit 10 - ADC oversampling mode managing interlaced conversions of ADC group regular and group injected"]
171 #[inline(always)]
172 pub fn rovsm(&mut self) -> ROVSM_W {
173 ROVSM_W { w: self }
174 }
175 #[doc = "Bit 9 - ADC oversampling discontinuous mode (triggered mode) for ADC group regular"]
176 #[inline(always)]
177 pub fn tovs(&mut self) -> TOVS_W {
178 TOVS_W { w: self }
179 }
180 #[doc = "Bits 5:8 - ADC oversampling shift"]
181 #[inline(always)]
182 pub fn ovss(&mut self) -> OVSS_W {
183 OVSS_W { w: self }
184 }
185 #[doc = "Bits 2:4 - ADC oversampling ratio"]
186 #[inline(always)]
187 pub fn ovsr(&mut self) -> OVSR_W {
188 OVSR_W { w: self }
189 }
190 #[doc = "Bit 1 - ADC oversampler enable on scope ADC group injected"]
191 #[inline(always)]
192 pub fn jovse(&mut self) -> JOVSE_W {
193 JOVSE_W { w: self }
194 }
195 #[doc = "Bit 0 - ADC oversampler enable on scope ADC group regular"]
196 #[inline(always)]
197 pub fn rovse(&mut self) -> ROVSE_W {
198 ROVSE_W { w: self }
199 }
200}