stm32wb_pac/tim2/
dcr.rs

1#[doc = "Reader of register DCR"]
2pub type R = crate::R<u32, super::DCR>;
3#[doc = "Writer for register DCR"]
4pub type W = crate::W<u32, super::DCR>;
5#[doc = "Register DCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::DCR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DBL`"]
14pub type DBL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `DBL`"]
16pub struct DBL_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DBL_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x1f << 8)) | (((value as u32) & 0x1f) << 8);
24        self.w
25    }
26}
27#[doc = "Reader of field `DBA`"]
28pub type DBA_R = crate::R<u8, u8>;
29#[doc = "Write proxy for field `DBA`"]
30pub struct DBA_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> DBA_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u8) -> &'a mut W {
37        self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
38        self.w
39    }
40}
41impl R {
42    #[doc = "Bits 8:12 - DMA burst length"]
43    #[inline(always)]
44    pub fn dbl(&self) -> DBL_R {
45        DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
46    }
47    #[doc = "Bits 0:4 - DMA base address"]
48    #[inline(always)]
49    pub fn dba(&self) -> DBA_R {
50        DBA_R::new((self.bits & 0x1f) as u8)
51    }
52}
53impl W {
54    #[doc = "Bits 8:12 - DMA burst length"]
55    #[inline(always)]
56    pub fn dbl(&mut self) -> DBL_W {
57        DBL_W { w: self }
58    }
59    #[doc = "Bits 0:4 - DMA base address"]
60    #[inline(always)]
61    pub fn dba(&mut self) -> DBA_W {
62        DBA_W { w: self }
63    }
64}
stm32wb_pac/tim2/dcr.rs

stm32wb_pac/tim2/
dcr.rs
