stm32wb_pac/rcc/
pllcfgr.rs

1#[doc = "Reader of register PLLCFGR"]
2pub type R = crate::R<u32, super::PLLCFGR>;
3#[doc = "Writer for register PLLCFGR"]
4pub type W = crate::W<u32, super::PLLCFGR>;
5#[doc = "Register PLLCFGR `reset()`'s with value 0x2204_0100"]
6impl crate::ResetValue for super::PLLCFGR {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x2204_0100
11    }
12}
13#[doc = "Reader of field `PLLR`"]
14pub type PLLR_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `PLLR`"]
16pub struct PLLR_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> PLLR_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29);
24        self.w
25    }
26}
27#[doc = "Reader of field `PLLREN`"]
28pub type PLLREN_R = crate::R<bool, bool>;
29#[doc = "Write proxy for field `PLLREN`"]
30pub struct PLLREN_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> PLLREN_W<'a> {
34    #[doc = r"Sets the field bit"]
35    #[inline(always)]
36    pub fn set_bit(self) -> &'a mut W {
37        self.bit(true)
38    }
39    #[doc = r"Clears the field bit"]
40    #[inline(always)]
41    pub fn clear_bit(self) -> &'a mut W {
42        self.bit(false)
43    }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
48        self.w
49    }
50}
51#[doc = "Reader of field `PLLQ`"]
52pub type PLLQ_R = crate::R<u8, u8>;
53#[doc = "Write proxy for field `PLLQ`"]
54pub struct PLLQ_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> PLLQ_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25);
62        self.w
63    }
64}
65#[doc = "Reader of field `PLLQEN`"]
66pub type PLLQEN_R = crate::R<bool, bool>;
67#[doc = "Write proxy for field `PLLQEN`"]
68pub struct PLLQEN_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> PLLQEN_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
86        self.w
87    }
88}
89#[doc = "Reader of field `PLLP`"]
90pub type PLLP_R = crate::R<u8, u8>;
91#[doc = "Write proxy for field `PLLP`"]
92pub struct PLLP_W<'a> {
93    w: &'a mut W,
94}
95impl<'a> PLLP_W<'a> {
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub unsafe fn bits(self, value: u8) -> &'a mut W {
99        self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17);
100        self.w
101    }
102}
103#[doc = "Reader of field `PLLPEN`"]
104pub type PLLPEN_R = crate::R<bool, bool>;
105#[doc = "Write proxy for field `PLLPEN`"]
106pub struct PLLPEN_W<'a> {
107    w: &'a mut W,
108}
109impl<'a> PLLPEN_W<'a> {
110    #[doc = r"Sets the field bit"]
111    #[inline(always)]
112    pub fn set_bit(self) -> &'a mut W {
113        self.bit(true)
114    }
115    #[doc = r"Clears the field bit"]
116    #[inline(always)]
117    pub fn clear_bit(self) -> &'a mut W {
118        self.bit(false)
119    }
120    #[doc = r"Writes raw bits to the field"]
121    #[inline(always)]
122    pub fn bit(self, value: bool) -> &'a mut W {
123        self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
124        self.w
125    }
126}
127#[doc = "Reader of field `PLLN`"]
128pub type PLLN_R = crate::R<u8, u8>;
129#[doc = "Write proxy for field `PLLN`"]
130pub struct PLLN_W<'a> {
131    w: &'a mut W,
132}
133impl<'a> PLLN_W<'a> {
134    #[doc = r"Writes raw bits to the field"]
135    #[inline(always)]
136    pub unsafe fn bits(self, value: u8) -> &'a mut W {
137        self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
138        self.w
139    }
140}
141#[doc = "Reader of field `PLLM`"]
142pub type PLLM_R = crate::R<u8, u8>;
143#[doc = "Write proxy for field `PLLM`"]
144pub struct PLLM_W<'a> {
145    w: &'a mut W,
146}
147impl<'a> PLLM_W<'a> {
148    #[doc = r"Writes raw bits to the field"]
149    #[inline(always)]
150    pub unsafe fn bits(self, value: u8) -> &'a mut W {
151        self.w.bits = (self.w.bits & !(0x07 << 4)) | (((value as u32) & 0x07) << 4);
152        self.w
153    }
154}
155#[doc = "Reader of field `PLLSRC`"]
156pub type PLLSRC_R = crate::R<u8, u8>;
157#[doc = "Write proxy for field `PLLSRC`"]
158pub struct PLLSRC_W<'a> {
159    w: &'a mut W,
160}
161impl<'a> PLLSRC_W<'a> {
162    #[doc = r"Writes raw bits to the field"]
163    #[inline(always)]
164    pub unsafe fn bits(self, value: u8) -> &'a mut W {
165        self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
166        self.w
167    }
168}
169impl R {
170    #[doc = "Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)"]
171    #[inline(always)]
172    pub fn pllr(&self) -> PLLR_R {
173        PLLR_R::new(((self.bits >> 29) & 0x07) as u8)
174    }
175    #[doc = "Bit 28 - Main PLLSYSR PLLCLK output enable"]
176    #[inline(always)]
177    pub fn pllren(&self) -> PLLREN_R {
178        PLLREN_R::new(((self.bits >> 28) & 0x01) != 0)
179    }
180    #[doc = "Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK"]
181    #[inline(always)]
182    pub fn pllq(&self) -> PLLQ_R {
183        PLLQ_R::new(((self.bits >> 25) & 0x07) as u8)
184    }
185    #[doc = "Bit 24 - Main PLLSYSQ output enable"]
186    #[inline(always)]
187    pub fn pllqen(&self) -> PLLQEN_R {
188        PLLQEN_R::new(((self.bits >> 24) & 0x01) != 0)
189    }
190    #[doc = "Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK"]
191    #[inline(always)]
192    pub fn pllp(&self) -> PLLP_R {
193        PLLP_R::new(((self.bits >> 17) & 0x1f) as u8)
194    }
195    #[doc = "Bit 16 - Main PLLSYSP output enable"]
196    #[inline(always)]
197    pub fn pllpen(&self) -> PLLPEN_R {
198        PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0)
199    }
200    #[doc = "Bits 8:14 - Main PLLSYS multiplication factor N"]
201    #[inline(always)]
202    pub fn plln(&self) -> PLLN_R {
203        PLLN_R::new(((self.bits >> 8) & 0x7f) as u8)
204    }
205    #[doc = "Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
206    #[inline(always)]
207    pub fn pllm(&self) -> PLLM_R {
208        PLLM_R::new(((self.bits >> 4) & 0x07) as u8)
209    }
210    #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
211    #[inline(always)]
212    pub fn pllsrc(&self) -> PLLSRC_R {
213        PLLSRC_R::new((self.bits & 0x03) as u8)
214    }
215}
216impl W {
217    #[doc = "Bits 29:31 - Main PLLSYS division factor R for SYSCLK (system clock)"]
218    #[inline(always)]
219    pub fn pllr(&mut self) -> PLLR_W {
220        PLLR_W { w: self }
221    }
222    #[doc = "Bit 28 - Main PLLSYSR PLLCLK output enable"]
223    #[inline(always)]
224    pub fn pllren(&mut self) -> PLLREN_W {
225        PLLREN_W { w: self }
226    }
227    #[doc = "Bits 25:27 - Main PLLSYS division factor Q for PLLSYSUSBCLK"]
228    #[inline(always)]
229    pub fn pllq(&mut self) -> PLLQ_W {
230        PLLQ_W { w: self }
231    }
232    #[doc = "Bit 24 - Main PLLSYSQ output enable"]
233    #[inline(always)]
234    pub fn pllqen(&mut self) -> PLLQEN_W {
235        PLLQEN_W { w: self }
236    }
237    #[doc = "Bits 17:21 - Main PLL division factor P for PPLSYSSAICLK"]
238    #[inline(always)]
239    pub fn pllp(&mut self) -> PLLP_W {
240        PLLP_W { w: self }
241    }
242    #[doc = "Bit 16 - Main PLLSYSP output enable"]
243    #[inline(always)]
244    pub fn pllpen(&mut self) -> PLLPEN_W {
245        PLLPEN_W { w: self }
246    }
247    #[doc = "Bits 8:14 - Main PLLSYS multiplication factor N"]
248    #[inline(always)]
249    pub fn plln(&mut self) -> PLLN_W {
250        PLLN_W { w: self }
251    }
252    #[doc = "Bits 4:6 - Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"]
253    #[inline(always)]
254    pub fn pllm(&mut self) -> PLLM_W {
255        PLLM_W { w: self }
256    }
257    #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"]
258    #[inline(always)]
259    pub fn pllsrc(&mut self) -> PLLSRC_W {
260        PLLSRC_W { w: self }
261    }
262}
stm32wb_pac/rcc/pllcfgr.rs

stm32wb_pac/rcc/
pllcfgr.rs
