stm32wb_pac/adc/
difsel.rs

1#[doc = "Reader of register DIFSEL"]
2pub type R = crate::R<u32, super::DIFSEL>;
3#[doc = "Writer for register DIFSEL"]
4pub type W = crate::W<u32, super::DIFSEL>;
5#[doc = "Register DIFSEL `reset()`'s with value 0"]
6impl crate::ResetValue for super::DIFSEL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIFSEL_0`"]
14pub type DIFSEL_0_R = crate::R<bool, bool>;
15#[doc = "Reader of field `DIFSEL_1_15`"]
16pub type DIFSEL_1_15_R = crate::R<u16, u16>;
17#[doc = "Write proxy for field `DIFSEL_1_15`"]
18pub struct DIFSEL_1_15_W<'a> {
19    w: &'a mut W,
20}
21impl<'a> DIFSEL_1_15_W<'a> {
22    #[doc = r"Writes raw bits to the field"]
23    #[inline(always)]
24    pub unsafe fn bits(self, value: u16) -> &'a mut W {
25        self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u32) & 0x7fff) << 1);
26        self.w
27    }
28}
29#[doc = "Reader of field `DIFSEL_16_18`"]
30pub type DIFSEL_16_18_R = crate::R<u8, u8>;
31impl R {
32    #[doc = "Bit 0 - ADC channel differential or single-ended mode for channel 0"]
33    #[inline(always)]
34    pub fn difsel_0(&self) -> DIFSEL_0_R {
35        DIFSEL_0_R::new((self.bits & 0x01) != 0)
36    }
37    #[doc = "Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15"]
38    #[inline(always)]
39    pub fn difsel_1_15(&self) -> DIFSEL_1_15_R {
40        DIFSEL_1_15_R::new(((self.bits >> 1) & 0x7fff) as u16)
41    }
42    #[doc = "Bits 16:18 - ADC channel differential or single-ended mode for channels 18 to 16"]
43    #[inline(always)]
44    pub fn difsel_16_18(&self) -> DIFSEL_16_18_R {
45        DIFSEL_16_18_R::new(((self.bits >> 16) & 0x07) as u8)
46    }
47}
48impl W {
49    #[doc = "Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15"]
50    #[inline(always)]
51    pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W {
52        DIFSEL_1_15_W { w: self }
53    }
54}
stm32wb_pac/adc/difsel.rs

stm32wb_pac/adc/
difsel.rs
