1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
#[doc = "Reader of register C2APB1FZR2"] pub type R = crate::R<u32, super::C2APB1FZR2>; #[doc = "Writer for register C2APB1FZR2"] pub type W = crate::W<u32, super::C2APB1FZR2>; #[doc = "Register C2APB1FZR2 `reset()`'s with value 0"] impl crate::ResetValue for super::C2APB1FZR2 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `DBG_LPTIM2_STOP`"] pub type DBG_LPTIM2_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_LPTIM2_STOP`"] pub struct DBG_LPTIM2_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_LPTIM2_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5); self.w } } impl R { #[doc = "Bit 5 - LPTIM2 counter stopped when core is halted"] #[inline(always)] pub fn dbg_lptim2_stop(&self) -> DBG_LPTIM2_STOP_R { DBG_LPTIM2_STOP_R::new(((self.bits >> 5) & 0x01) != 0) } } impl W { #[doc = "Bit 5 - LPTIM2 counter stopped when core is halted"] #[inline(always)] pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W { DBG_LPTIM2_STOP_W { w: self } } }