stm32u5/stm32u545/dac1/
mcr.rs

1///Register `MCR` reader
2pub type R = crate::R<MCRrs>;
3///Register `MCR` writer
4pub type W = crate::W<MCRrs>;
5/**DAC channel%s mode
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum MODE1 {
12    ///0: Normal mode - DAC channelx is connected to external pin with Buffer enabled
13    NormalPinBuffer = 0,
14    ///1: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
15    NormalPinChipBuffer = 1,
16    ///2: Normal mode - DAC channelx is connected to external pin with Buffer disabled
17    NormalPinNoBuffer = 2,
18    ///3: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
19    NormalChipNoBuffer = 3,
20    ///4: S&H mode - DAC channelx is connected to external pin with Buffer enabled
21    ShpinBuffer = 4,
22    ///5: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
23    ShpinChipBuffer = 5,
24    ///6: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
25    ShpinNoBuffer = 6,
26    ///7: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
27    ShchipNoBuffer = 7,
28}
29impl From<MODE1> for u8 {
30    #[inline(always)]
31    fn from(variant: MODE1) -> Self {
32        variant as _
33    }
34}
35impl crate::FieldSpec for MODE1 {
36    type Ux = u8;
37}
38impl crate::IsEnum for MODE1 {}
39///Field `MODE(1-2)` reader - DAC channel%s mode
40pub type MODE_R = crate::FieldReader<MODE1>;
41impl MODE_R {
42    ///Get enumerated values variant
43    #[inline(always)]
44    pub const fn variant(&self) -> MODE1 {
45        match self.bits {
46            0 => MODE1::NormalPinBuffer,
47            1 => MODE1::NormalPinChipBuffer,
48            2 => MODE1::NormalPinNoBuffer,
49            3 => MODE1::NormalChipNoBuffer,
50            4 => MODE1::ShpinBuffer,
51            5 => MODE1::ShpinChipBuffer,
52            6 => MODE1::ShpinNoBuffer,
53            7 => MODE1::ShchipNoBuffer,
54            _ => unreachable!(),
55        }
56    }
57    ///Normal mode - DAC channelx is connected to external pin with Buffer enabled
58    #[inline(always)]
59    pub fn is_normal_pin_buffer(&self) -> bool {
60        *self == MODE1::NormalPinBuffer
61    }
62    ///Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
63    #[inline(always)]
64    pub fn is_normal_pin_chip_buffer(&self) -> bool {
65        *self == MODE1::NormalPinChipBuffer
66    }
67    ///Normal mode - DAC channelx is connected to external pin with Buffer disabled
68    #[inline(always)]
69    pub fn is_normal_pin_no_buffer(&self) -> bool {
70        *self == MODE1::NormalPinNoBuffer
71    }
72    ///Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
73    #[inline(always)]
74    pub fn is_normal_chip_no_buffer(&self) -> bool {
75        *self == MODE1::NormalChipNoBuffer
76    }
77    ///S&H mode - DAC channelx is connected to external pin with Buffer enabled
78    #[inline(always)]
79    pub fn is_shpin_buffer(&self) -> bool {
80        *self == MODE1::ShpinBuffer
81    }
82    ///S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
83    #[inline(always)]
84    pub fn is_shpin_chip_buffer(&self) -> bool {
85        *self == MODE1::ShpinChipBuffer
86    }
87    ///S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
88    #[inline(always)]
89    pub fn is_shpin_no_buffer(&self) -> bool {
90        *self == MODE1::ShpinNoBuffer
91    }
92    ///S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
93    #[inline(always)]
94    pub fn is_shchip_no_buffer(&self) -> bool {
95        *self == MODE1::ShchipNoBuffer
96    }
97}
98///Field `MODE(1-2)` writer - DAC channel%s mode
99pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MODE1, crate::Safe>;
100impl<'a, REG> MODE_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103    REG::Ux: From<u8>,
104{
105    ///Normal mode - DAC channelx is connected to external pin with Buffer enabled
106    #[inline(always)]
107    pub fn normal_pin_buffer(self) -> &'a mut crate::W<REG> {
108        self.variant(MODE1::NormalPinBuffer)
109    }
110    ///Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
111    #[inline(always)]
112    pub fn normal_pin_chip_buffer(self) -> &'a mut crate::W<REG> {
113        self.variant(MODE1::NormalPinChipBuffer)
114    }
115    ///Normal mode - DAC channelx is connected to external pin with Buffer disabled
116    #[inline(always)]
117    pub fn normal_pin_no_buffer(self) -> &'a mut crate::W<REG> {
118        self.variant(MODE1::NormalPinNoBuffer)
119    }
120    ///Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
121    #[inline(always)]
122    pub fn normal_chip_no_buffer(self) -> &'a mut crate::W<REG> {
123        self.variant(MODE1::NormalChipNoBuffer)
124    }
125    ///S&H mode - DAC channelx is connected to external pin with Buffer enabled
126    #[inline(always)]
127    pub fn shpin_buffer(self) -> &'a mut crate::W<REG> {
128        self.variant(MODE1::ShpinBuffer)
129    }
130    ///S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
131    #[inline(always)]
132    pub fn shpin_chip_buffer(self) -> &'a mut crate::W<REG> {
133        self.variant(MODE1::ShpinChipBuffer)
134    }
135    ///S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
136    #[inline(always)]
137    pub fn shpin_no_buffer(self) -> &'a mut crate::W<REG> {
138        self.variant(MODE1::ShpinNoBuffer)
139    }
140    ///S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled
141    #[inline(always)]
142    pub fn shchip_no_buffer(self) -> &'a mut crate::W<REG> {
143        self.variant(MODE1::ShchipNoBuffer)
144    }
145}
146/**DAC channel%s DMA double data mode
147
148Value on reset: 0*/
149#[cfg_attr(feature = "defmt", derive(defmt::Format))]
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151pub enum DMADOUBLE1 {
152    ///0: DMA Normal mode selected
153    Normal = 0,
154    ///1: DMA Double data mode selected
155    DoubleData = 1,
156}
157impl From<DMADOUBLE1> for bool {
158    #[inline(always)]
159    fn from(variant: DMADOUBLE1) -> Self {
160        variant as u8 != 0
161    }
162}
163///Field `DMADOUBLE(1-2)` reader - DAC channel%s DMA double data mode
164pub type DMADOUBLE_R = crate::BitReader<DMADOUBLE1>;
165impl DMADOUBLE_R {
166    ///Get enumerated values variant
167    #[inline(always)]
168    pub const fn variant(&self) -> DMADOUBLE1 {
169        match self.bits {
170            false => DMADOUBLE1::Normal,
171            true => DMADOUBLE1::DoubleData,
172        }
173    }
174    ///DMA Normal mode selected
175    #[inline(always)]
176    pub fn is_normal(&self) -> bool {
177        *self == DMADOUBLE1::Normal
178    }
179    ///DMA Double data mode selected
180    #[inline(always)]
181    pub fn is_double_data(&self) -> bool {
182        *self == DMADOUBLE1::DoubleData
183    }
184}
185///Field `DMADOUBLE(1-2)` writer - DAC channel%s DMA double data mode
186pub type DMADOUBLE_W<'a, REG> = crate::BitWriter<'a, REG, DMADOUBLE1>;
187impl<'a, REG> DMADOUBLE_W<'a, REG>
188where
189    REG: crate::Writable + crate::RegisterSpec,
190{
191    ///DMA Normal mode selected
192    #[inline(always)]
193    pub fn normal(self) -> &'a mut crate::W<REG> {
194        self.variant(DMADOUBLE1::Normal)
195    }
196    ///DMA Double data mode selected
197    #[inline(always)]
198    pub fn double_data(self) -> &'a mut crate::W<REG> {
199        self.variant(DMADOUBLE1::DoubleData)
200    }
201}
202/**Enable signed format for DAC channel%s
203
204Value on reset: 0*/
205#[cfg_attr(feature = "defmt", derive(defmt::Format))]
206#[derive(Clone, Copy, Debug, PartialEq, Eq)]
207pub enum SINFORMAT1 {
208    ///0: Input data is in unsigned format
209    Unsigned = 0,
210    ///1: Input data is in signed format (2's complement). The MSB bit represents the sign.
211    Signed = 1,
212}
213impl From<SINFORMAT1> for bool {
214    #[inline(always)]
215    fn from(variant: SINFORMAT1) -> Self {
216        variant as u8 != 0
217    }
218}
219///Field `SINFORMAT(1-2)` reader - Enable signed format for DAC channel%s
220pub type SINFORMAT_R = crate::BitReader<SINFORMAT1>;
221impl SINFORMAT_R {
222    ///Get enumerated values variant
223    #[inline(always)]
224    pub const fn variant(&self) -> SINFORMAT1 {
225        match self.bits {
226            false => SINFORMAT1::Unsigned,
227            true => SINFORMAT1::Signed,
228        }
229    }
230    ///Input data is in unsigned format
231    #[inline(always)]
232    pub fn is_unsigned(&self) -> bool {
233        *self == SINFORMAT1::Unsigned
234    }
235    ///Input data is in signed format (2's complement). The MSB bit represents the sign.
236    #[inline(always)]
237    pub fn is_signed(&self) -> bool {
238        *self == SINFORMAT1::Signed
239    }
240}
241///Field `SINFORMAT(1-2)` writer - Enable signed format for DAC channel%s
242pub type SINFORMAT_W<'a, REG> = crate::BitWriter<'a, REG, SINFORMAT1>;
243impl<'a, REG> SINFORMAT_W<'a, REG>
244where
245    REG: crate::Writable + crate::RegisterSpec,
246{
247    ///Input data is in unsigned format
248    #[inline(always)]
249    pub fn unsigned(self) -> &'a mut crate::W<REG> {
250        self.variant(SINFORMAT1::Unsigned)
251    }
252    ///Input data is in signed format (2's complement). The MSB bit represents the sign.
253    #[inline(always)]
254    pub fn signed(self) -> &'a mut crate::W<REG> {
255        self.variant(SINFORMAT1::Signed)
256    }
257}
258/**High frequency interface mode selection
259
260Value on reset: 0*/
261#[cfg_attr(feature = "defmt", derive(defmt::Format))]
262#[derive(Clone, Copy, Debug, PartialEq, Eq)]
263#[repr(u8)]
264pub enum HFSEL {
265    ///0: High frequency interface mode disabled
266    Disabled = 0,
267    ///1: High frequency interface mode enabled for AHB clock frequency > 80 MHz
268    More80mhz = 1,
269    ///2: High frequency interface mode enabled for AHB clock frequency >160 MHz
270    More160mhz = 2,
271}
272impl From<HFSEL> for u8 {
273    #[inline(always)]
274    fn from(variant: HFSEL) -> Self {
275        variant as _
276    }
277}
278impl crate::FieldSpec for HFSEL {
279    type Ux = u8;
280}
281impl crate::IsEnum for HFSEL {}
282///Field `HFSEL` reader - High frequency interface mode selection
283pub type HFSEL_R = crate::FieldReader<HFSEL>;
284impl HFSEL_R {
285    ///Get enumerated values variant
286    #[inline(always)]
287    pub const fn variant(&self) -> Option<HFSEL> {
288        match self.bits {
289            0 => Some(HFSEL::Disabled),
290            1 => Some(HFSEL::More80mhz),
291            2 => Some(HFSEL::More160mhz),
292            _ => None,
293        }
294    }
295    ///High frequency interface mode disabled
296    #[inline(always)]
297    pub fn is_disabled(&self) -> bool {
298        *self == HFSEL::Disabled
299    }
300    ///High frequency interface mode enabled for AHB clock frequency > 80 MHz
301    #[inline(always)]
302    pub fn is_more80mhz(&self) -> bool {
303        *self == HFSEL::More80mhz
304    }
305    ///High frequency interface mode enabled for AHB clock frequency >160 MHz
306    #[inline(always)]
307    pub fn is_more160mhz(&self) -> bool {
308        *self == HFSEL::More160mhz
309    }
310}
311///Field `HFSEL` writer - High frequency interface mode selection
312pub type HFSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, HFSEL>;
313impl<'a, REG> HFSEL_W<'a, REG>
314where
315    REG: crate::Writable + crate::RegisterSpec,
316    REG::Ux: From<u8>,
317{
318    ///High frequency interface mode disabled
319    #[inline(always)]
320    pub fn disabled(self) -> &'a mut crate::W<REG> {
321        self.variant(HFSEL::Disabled)
322    }
323    ///High frequency interface mode enabled for AHB clock frequency > 80 MHz
324    #[inline(always)]
325    pub fn more80mhz(self) -> &'a mut crate::W<REG> {
326        self.variant(HFSEL::More80mhz)
327    }
328    ///High frequency interface mode enabled for AHB clock frequency >160 MHz
329    #[inline(always)]
330    pub fn more160mhz(self) -> &'a mut crate::W<REG> {
331        self.variant(HFSEL::More160mhz)
332    }
333}
334impl R {
335    ///DAC channel(1-2) mode
336    ///
337    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE1` field.</div>
338    #[inline(always)]
339    pub fn mode(&self, n: u8) -> MODE_R {
340        #[allow(clippy::no_effect)]
341        [(); 2][n as usize];
342        MODE_R::new(((self.bits >> (n * 16)) & 7) as u8)
343    }
344    ///Iterator for array of:
345    ///DAC channel(1-2) mode
346    #[inline(always)]
347    pub fn mode_iter(&self) -> impl Iterator<Item = MODE_R> + '_ {
348        (0..2).map(move |n| MODE_R::new(((self.bits >> (n * 16)) & 7) as u8))
349    }
350    ///Bits 0:2 - DAC channel1 mode
351    #[inline(always)]
352    pub fn mode1(&self) -> MODE_R {
353        MODE_R::new((self.bits & 7) as u8)
354    }
355    ///Bits 16:18 - DAC channel2 mode
356    #[inline(always)]
357    pub fn mode2(&self) -> MODE_R {
358        MODE_R::new(((self.bits >> 16) & 7) as u8)
359    }
360    ///DAC channel(1-2) DMA double data mode
361    ///
362    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DMADOUBLE1` field.</div>
363    #[inline(always)]
364    pub fn dmadouble(&self, n: u8) -> DMADOUBLE_R {
365        #[allow(clippy::no_effect)]
366        [(); 2][n as usize];
367        DMADOUBLE_R::new(((self.bits >> (n * 16 + 8)) & 1) != 0)
368    }
369    ///Iterator for array of:
370    ///DAC channel(1-2) DMA double data mode
371    #[inline(always)]
372    pub fn dmadouble_iter(&self) -> impl Iterator<Item = DMADOUBLE_R> + '_ {
373        (0..2).map(move |n| DMADOUBLE_R::new(((self.bits >> (n * 16 + 8)) & 1) != 0))
374    }
375    ///Bit 8 - DAC channel1 DMA double data mode
376    #[inline(always)]
377    pub fn dmadouble1(&self) -> DMADOUBLE_R {
378        DMADOUBLE_R::new(((self.bits >> 8) & 1) != 0)
379    }
380    ///Bit 24 - DAC channel2 DMA double data mode
381    #[inline(always)]
382    pub fn dmadouble2(&self) -> DMADOUBLE_R {
383        DMADOUBLE_R::new(((self.bits >> 24) & 1) != 0)
384    }
385    ///Enable signed format for DAC channel(1-2)
386    ///
387    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SINFORMAT1` field.</div>
388    #[inline(always)]
389    pub fn sinformat(&self, n: u8) -> SINFORMAT_R {
390        #[allow(clippy::no_effect)]
391        [(); 2][n as usize];
392        SINFORMAT_R::new(((self.bits >> (n * 16 + 9)) & 1) != 0)
393    }
394    ///Iterator for array of:
395    ///Enable signed format for DAC channel(1-2)
396    #[inline(always)]
397    pub fn sinformat_iter(&self) -> impl Iterator<Item = SINFORMAT_R> + '_ {
398        (0..2).map(move |n| SINFORMAT_R::new(((self.bits >> (n * 16 + 9)) & 1) != 0))
399    }
400    ///Bit 9 - Enable signed format for DAC channel1
401    #[inline(always)]
402    pub fn sinformat1(&self) -> SINFORMAT_R {
403        SINFORMAT_R::new(((self.bits >> 9) & 1) != 0)
404    }
405    ///Bit 25 - Enable signed format for DAC channel2
406    #[inline(always)]
407    pub fn sinformat2(&self) -> SINFORMAT_R {
408        SINFORMAT_R::new(((self.bits >> 25) & 1) != 0)
409    }
410    ///Bits 14:15 - High frequency interface mode selection
411    #[inline(always)]
412    pub fn hfsel(&self) -> HFSEL_R {
413        HFSEL_R::new(((self.bits >> 14) & 3) as u8)
414    }
415}
416impl core::fmt::Debug for R {
417    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
418        f.debug_struct("MCR")
419            .field("mode1", &self.mode1())
420            .field("mode2", &self.mode2())
421            .field("dmadouble1", &self.dmadouble1())
422            .field("dmadouble2", &self.dmadouble2())
423            .field("sinformat1", &self.sinformat1())
424            .field("sinformat2", &self.sinformat2())
425            .field("hfsel", &self.hfsel())
426            .finish()
427    }
428}
429impl W {
430    ///DAC channel(1-2) mode
431    ///
432    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MODE1` field.</div>
433    #[inline(always)]
434    pub fn mode(&mut self, n: u8) -> MODE_W<MCRrs> {
435        #[allow(clippy::no_effect)]
436        [(); 2][n as usize];
437        MODE_W::new(self, n * 16)
438    }
439    ///Bits 0:2 - DAC channel1 mode
440    #[inline(always)]
441    pub fn mode1(&mut self) -> MODE_W<MCRrs> {
442        MODE_W::new(self, 0)
443    }
444    ///Bits 16:18 - DAC channel2 mode
445    #[inline(always)]
446    pub fn mode2(&mut self) -> MODE_W<MCRrs> {
447        MODE_W::new(self, 16)
448    }
449    ///DAC channel(1-2) DMA double data mode
450    ///
451    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `DMADOUBLE1` field.</div>
452    #[inline(always)]
453    pub fn dmadouble(&mut self, n: u8) -> DMADOUBLE_W<MCRrs> {
454        #[allow(clippy::no_effect)]
455        [(); 2][n as usize];
456        DMADOUBLE_W::new(self, n * 16 + 8)
457    }
458    ///Bit 8 - DAC channel1 DMA double data mode
459    #[inline(always)]
460    pub fn dmadouble1(&mut self) -> DMADOUBLE_W<MCRrs> {
461        DMADOUBLE_W::new(self, 8)
462    }
463    ///Bit 24 - DAC channel2 DMA double data mode
464    #[inline(always)]
465    pub fn dmadouble2(&mut self) -> DMADOUBLE_W<MCRrs> {
466        DMADOUBLE_W::new(self, 24)
467    }
468    ///Enable signed format for DAC channel(1-2)
469    ///
470    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SINFORMAT1` field.</div>
471    #[inline(always)]
472    pub fn sinformat(&mut self, n: u8) -> SINFORMAT_W<MCRrs> {
473        #[allow(clippy::no_effect)]
474        [(); 2][n as usize];
475        SINFORMAT_W::new(self, n * 16 + 9)
476    }
477    ///Bit 9 - Enable signed format for DAC channel1
478    #[inline(always)]
479    pub fn sinformat1(&mut self) -> SINFORMAT_W<MCRrs> {
480        SINFORMAT_W::new(self, 9)
481    }
482    ///Bit 25 - Enable signed format for DAC channel2
483    #[inline(always)]
484    pub fn sinformat2(&mut self) -> SINFORMAT_W<MCRrs> {
485        SINFORMAT_W::new(self, 25)
486    }
487    ///Bits 14:15 - High frequency interface mode selection
488    #[inline(always)]
489    pub fn hfsel(&mut self) -> HFSEL_W<MCRrs> {
490        HFSEL_W::new(self, 14)
491    }
492}
493/**DAC mode control register
494
495You can [`read`](crate::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
496
497See register [structure](https://stm32-rs.github.io/stm32-rs/STM32U545.html#DAC1:MCR)*/
498pub struct MCRrs;
499impl crate::RegisterSpec for MCRrs {
500    type Ux = u32;
501}
502///`read()` method returns [`mcr::R`](R) reader structure
503impl crate::Readable for MCRrs {}
504///`write(|w| ..)` method takes [`mcr::W`](W) writer structure
505impl crate::Writable for MCRrs {
506    type Safety = crate::Unsafe;
507}
508///`reset()` method sets MCR to value 0
509impl crate::Resettable for MCRrs {}
stm32u5/stm32u545/dac1/mcr.rs

stm32u5/stm32u545/dac1/
mcr.rs
