stm32ral/stm32l4/peripherals/tsc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Touch sensing controller
4//!
5//! Used by: stm32l412, stm32l4r5, stm32l4r9, stm32l4x1, stm32l4x2, stm32l4x3, stm32l4x5, stm32l4x6
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register
12pub mod CR {
13
14 /// Charge transfer pulse high
15 pub mod CTPH {
16 /// Offset (28 bits)
17 pub const offset: u32 = 28;
18 /// Mask (4 bits: 0b1111 << 28)
19 pub const mask: u32 = 0b1111 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values (empty)
25 pub mod RW {}
26 }
27
28 /// Charge transfer pulse low
29 pub mod CTPL {
30 /// Offset (24 bits)
31 pub const offset: u32 = 24;
32 /// Mask (4 bits: 0b1111 << 24)
33 pub const mask: u32 = 0b1111 << offset;
34 /// Read-only values (empty)
35 pub mod R {}
36 /// Write-only values (empty)
37 pub mod W {}
38 /// Read-write values (empty)
39 pub mod RW {}
40 }
41
42 /// Spread spectrum deviation
43 pub mod SSD {
44 /// Offset (17 bits)
45 pub const offset: u32 = 17;
46 /// Mask (7 bits: 0x7f << 17)
47 pub const mask: u32 = 0x7f << offset;
48 /// Read-only values (empty)
49 pub mod R {}
50 /// Write-only values (empty)
51 pub mod W {}
52 /// Read-write values (empty)
53 pub mod RW {}
54 }
55
56 /// Spread spectrum enable
57 pub mod SSE {
58 /// Offset (16 bits)
59 pub const offset: u32 = 16;
60 /// Mask (1 bit: 1 << 16)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values (empty)
67 pub mod RW {}
68 }
69
70 /// Spread spectrum prescaler
71 pub mod SSPSC {
72 /// Offset (15 bits)
73 pub const offset: u32 = 15;
74 /// Mask (1 bit: 1 << 15)
75 pub const mask: u32 = 1 << offset;
76 /// Read-only values (empty)
77 pub mod R {}
78 /// Write-only values (empty)
79 pub mod W {}
80 /// Read-write values (empty)
81 pub mod RW {}
82 }
83
84 /// pulse generator prescaler
85 pub mod PGPSC {
86 /// Offset (12 bits)
87 pub const offset: u32 = 12;
88 /// Mask (3 bits: 0b111 << 12)
89 pub const mask: u32 = 0b111 << offset;
90 /// Read-only values (empty)
91 pub mod R {}
92 /// Write-only values (empty)
93 pub mod W {}
94 /// Read-write values (empty)
95 pub mod RW {}
96 }
97
98 /// Max count value
99 pub mod MCV {
100 /// Offset (5 bits)
101 pub const offset: u32 = 5;
102 /// Mask (3 bits: 0b111 << 5)
103 pub const mask: u32 = 0b111 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values (empty)
109 pub mod RW {}
110 }
111
112 /// I/O Default mode
113 pub mod IODEF {
114 /// Offset (4 bits)
115 pub const offset: u32 = 4;
116 /// Mask (1 bit: 1 << 4)
117 pub const mask: u32 = 1 << offset;
118 /// Read-only values (empty)
119 pub mod R {}
120 /// Write-only values (empty)
121 pub mod W {}
122 /// Read-write values (empty)
123 pub mod RW {}
124 }
125
126 /// Synchronization pin polarity
127 pub mod SYNCPOL {
128 /// Offset (3 bits)
129 pub const offset: u32 = 3;
130 /// Mask (1 bit: 1 << 3)
131 pub const mask: u32 = 1 << offset;
132 /// Read-only values (empty)
133 pub mod R {}
134 /// Write-only values (empty)
135 pub mod W {}
136 /// Read-write values (empty)
137 pub mod RW {}
138 }
139
140 /// Acquisition mode
141 pub mod AM {
142 /// Offset (2 bits)
143 pub const offset: u32 = 2;
144 /// Mask (1 bit: 1 << 2)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values (empty)
151 pub mod RW {}
152 }
153
154 /// Start a new acquisition
155 pub mod START {
156 /// Offset (1 bits)
157 pub const offset: u32 = 1;
158 /// Mask (1 bit: 1 << 1)
159 pub const mask: u32 = 1 << offset;
160 /// Read-only values (empty)
161 pub mod R {}
162 /// Write-only values (empty)
163 pub mod W {}
164 /// Read-write values (empty)
165 pub mod RW {}
166 }
167
168 /// Touch sensing controller enable
169 pub mod TSCE {
170 /// Offset (0 bits)
171 pub const offset: u32 = 0;
172 /// Mask (1 bit: 1 << 0)
173 pub const mask: u32 = 1 << offset;
174 /// Read-only values (empty)
175 pub mod R {}
176 /// Write-only values (empty)
177 pub mod W {}
178 /// Read-write values (empty)
179 pub mod RW {}
180 }
181}
182
183/// interrupt enable register
184pub mod IER {
185
186 /// Max count error interrupt enable
187 pub mod MCEIE {
188 /// Offset (1 bits)
189 pub const offset: u32 = 1;
190 /// Mask (1 bit: 1 << 1)
191 pub const mask: u32 = 1 << offset;
192 /// Read-only values (empty)
193 pub mod R {}
194 /// Write-only values (empty)
195 pub mod W {}
196 /// Read-write values (empty)
197 pub mod RW {}
198 }
199
200 /// End of acquisition interrupt enable
201 pub mod EOAIE {
202 /// Offset (0 bits)
203 pub const offset: u32 = 0;
204 /// Mask (1 bit: 1 << 0)
205 pub const mask: u32 = 1 << offset;
206 /// Read-only values (empty)
207 pub mod R {}
208 /// Write-only values (empty)
209 pub mod W {}
210 /// Read-write values (empty)
211 pub mod RW {}
212 }
213}
214
215/// interrupt clear register
216pub mod ICR {
217
218 /// Max count error interrupt clear
219 pub mod MCEIC {
220 /// Offset (1 bits)
221 pub const offset: u32 = 1;
222 /// Mask (1 bit: 1 << 1)
223 pub const mask: u32 = 1 << offset;
224 /// Read-only values (empty)
225 pub mod R {}
226 /// Write-only values (empty)
227 pub mod W {}
228 /// Read-write values (empty)
229 pub mod RW {}
230 }
231
232 /// End of acquisition interrupt clear
233 pub mod EOAIC {
234 /// Offset (0 bits)
235 pub const offset: u32 = 0;
236 /// Mask (1 bit: 1 << 0)
237 pub const mask: u32 = 1 << offset;
238 /// Read-only values (empty)
239 pub mod R {}
240 /// Write-only values (empty)
241 pub mod W {}
242 /// Read-write values (empty)
243 pub mod RW {}
244 }
245}
246
247/// interrupt status register
248pub mod ISR {
249
250 /// Max count error flag
251 pub mod MCEF {
252 /// Offset (1 bits)
253 pub const offset: u32 = 1;
254 /// Mask (1 bit: 1 << 1)
255 pub const mask: u32 = 1 << offset;
256 /// Read-only values (empty)
257 pub mod R {}
258 /// Write-only values (empty)
259 pub mod W {}
260 /// Read-write values (empty)
261 pub mod RW {}
262 }
263
264 /// End of acquisition flag
265 pub mod EOAF {
266 /// Offset (0 bits)
267 pub const offset: u32 = 0;
268 /// Mask (1 bit: 1 << 0)
269 pub const mask: u32 = 1 << offset;
270 /// Read-only values (empty)
271 pub mod R {}
272 /// Write-only values (empty)
273 pub mod W {}
274 /// Read-write values (empty)
275 pub mod RW {}
276 }
277}
278
279/// I/O hysteresis control register
280pub mod IOHCR {
281
282 /// G8_IO4
283 pub mod G8_IO4 {
284 /// Offset (31 bits)
285 pub const offset: u32 = 31;
286 /// Mask (1 bit: 1 << 31)
287 pub const mask: u32 = 1 << offset;
288 /// Read-only values (empty)
289 pub mod R {}
290 /// Write-only values (empty)
291 pub mod W {}
292 /// Read-write values (empty)
293 pub mod RW {}
294 }
295
296 /// G8_IO3
297 pub mod G8_IO3 {
298 /// Offset (30 bits)
299 pub const offset: u32 = 30;
300 /// Mask (1 bit: 1 << 30)
301 pub const mask: u32 = 1 << offset;
302 /// Read-only values (empty)
303 pub mod R {}
304 /// Write-only values (empty)
305 pub mod W {}
306 /// Read-write values (empty)
307 pub mod RW {}
308 }
309
310 /// G8_IO2
311 pub mod G8_IO2 {
312 /// Offset (29 bits)
313 pub const offset: u32 = 29;
314 /// Mask (1 bit: 1 << 29)
315 pub const mask: u32 = 1 << offset;
316 /// Read-only values (empty)
317 pub mod R {}
318 /// Write-only values (empty)
319 pub mod W {}
320 /// Read-write values (empty)
321 pub mod RW {}
322 }
323
324 /// G8_IO1
325 pub mod G8_IO1 {
326 /// Offset (28 bits)
327 pub const offset: u32 = 28;
328 /// Mask (1 bit: 1 << 28)
329 pub const mask: u32 = 1 << offset;
330 /// Read-only values (empty)
331 pub mod R {}
332 /// Write-only values (empty)
333 pub mod W {}
334 /// Read-write values (empty)
335 pub mod RW {}
336 }
337
338 /// G7_IO4
339 pub mod G7_IO4 {
340 /// Offset (27 bits)
341 pub const offset: u32 = 27;
342 /// Mask (1 bit: 1 << 27)
343 pub const mask: u32 = 1 << offset;
344 /// Read-only values (empty)
345 pub mod R {}
346 /// Write-only values (empty)
347 pub mod W {}
348 /// Read-write values (empty)
349 pub mod RW {}
350 }
351
352 /// G7_IO3
353 pub mod G7_IO3 {
354 /// Offset (26 bits)
355 pub const offset: u32 = 26;
356 /// Mask (1 bit: 1 << 26)
357 pub const mask: u32 = 1 << offset;
358 /// Read-only values (empty)
359 pub mod R {}
360 /// Write-only values (empty)
361 pub mod W {}
362 /// Read-write values (empty)
363 pub mod RW {}
364 }
365
366 /// G7_IO2
367 pub mod G7_IO2 {
368 /// Offset (25 bits)
369 pub const offset: u32 = 25;
370 /// Mask (1 bit: 1 << 25)
371 pub const mask: u32 = 1 << offset;
372 /// Read-only values (empty)
373 pub mod R {}
374 /// Write-only values (empty)
375 pub mod W {}
376 /// Read-write values (empty)
377 pub mod RW {}
378 }
379
380 /// G7_IO1
381 pub mod G7_IO1 {
382 /// Offset (24 bits)
383 pub const offset: u32 = 24;
384 /// Mask (1 bit: 1 << 24)
385 pub const mask: u32 = 1 << offset;
386 /// Read-only values (empty)
387 pub mod R {}
388 /// Write-only values (empty)
389 pub mod W {}
390 /// Read-write values (empty)
391 pub mod RW {}
392 }
393
394 /// G6_IO4
395 pub mod G6_IO4 {
396 /// Offset (23 bits)
397 pub const offset: u32 = 23;
398 /// Mask (1 bit: 1 << 23)
399 pub const mask: u32 = 1 << offset;
400 /// Read-only values (empty)
401 pub mod R {}
402 /// Write-only values (empty)
403 pub mod W {}
404 /// Read-write values (empty)
405 pub mod RW {}
406 }
407
408 /// G6_IO3
409 pub mod G6_IO3 {
410 /// Offset (22 bits)
411 pub const offset: u32 = 22;
412 /// Mask (1 bit: 1 << 22)
413 pub const mask: u32 = 1 << offset;
414 /// Read-only values (empty)
415 pub mod R {}
416 /// Write-only values (empty)
417 pub mod W {}
418 /// Read-write values (empty)
419 pub mod RW {}
420 }
421
422 /// G6_IO2
423 pub mod G6_IO2 {
424 /// Offset (21 bits)
425 pub const offset: u32 = 21;
426 /// Mask (1 bit: 1 << 21)
427 pub const mask: u32 = 1 << offset;
428 /// Read-only values (empty)
429 pub mod R {}
430 /// Write-only values (empty)
431 pub mod W {}
432 /// Read-write values (empty)
433 pub mod RW {}
434 }
435
436 /// G6_IO1
437 pub mod G6_IO1 {
438 /// Offset (20 bits)
439 pub const offset: u32 = 20;
440 /// Mask (1 bit: 1 << 20)
441 pub const mask: u32 = 1 << offset;
442 /// Read-only values (empty)
443 pub mod R {}
444 /// Write-only values (empty)
445 pub mod W {}
446 /// Read-write values (empty)
447 pub mod RW {}
448 }
449
450 /// G5_IO4
451 pub mod G5_IO4 {
452 /// Offset (19 bits)
453 pub const offset: u32 = 19;
454 /// Mask (1 bit: 1 << 19)
455 pub const mask: u32 = 1 << offset;
456 /// Read-only values (empty)
457 pub mod R {}
458 /// Write-only values (empty)
459 pub mod W {}
460 /// Read-write values (empty)
461 pub mod RW {}
462 }
463
464 /// G5_IO3
465 pub mod G5_IO3 {
466 /// Offset (18 bits)
467 pub const offset: u32 = 18;
468 /// Mask (1 bit: 1 << 18)
469 pub const mask: u32 = 1 << offset;
470 /// Read-only values (empty)
471 pub mod R {}
472 /// Write-only values (empty)
473 pub mod W {}
474 /// Read-write values (empty)
475 pub mod RW {}
476 }
477
478 /// G5_IO2
479 pub mod G5_IO2 {
480 /// Offset (17 bits)
481 pub const offset: u32 = 17;
482 /// Mask (1 bit: 1 << 17)
483 pub const mask: u32 = 1 << offset;
484 /// Read-only values (empty)
485 pub mod R {}
486 /// Write-only values (empty)
487 pub mod W {}
488 /// Read-write values (empty)
489 pub mod RW {}
490 }
491
492 /// G5_IO1
493 pub mod G5_IO1 {
494 /// Offset (16 bits)
495 pub const offset: u32 = 16;
496 /// Mask (1 bit: 1 << 16)
497 pub const mask: u32 = 1 << offset;
498 /// Read-only values (empty)
499 pub mod R {}
500 /// Write-only values (empty)
501 pub mod W {}
502 /// Read-write values (empty)
503 pub mod RW {}
504 }
505
506 /// G4_IO4
507 pub mod G4_IO4 {
508 /// Offset (15 bits)
509 pub const offset: u32 = 15;
510 /// Mask (1 bit: 1 << 15)
511 pub const mask: u32 = 1 << offset;
512 /// Read-only values (empty)
513 pub mod R {}
514 /// Write-only values (empty)
515 pub mod W {}
516 /// Read-write values (empty)
517 pub mod RW {}
518 }
519
520 /// G4_IO3
521 pub mod G4_IO3 {
522 /// Offset (14 bits)
523 pub const offset: u32 = 14;
524 /// Mask (1 bit: 1 << 14)
525 pub const mask: u32 = 1 << offset;
526 /// Read-only values (empty)
527 pub mod R {}
528 /// Write-only values (empty)
529 pub mod W {}
530 /// Read-write values (empty)
531 pub mod RW {}
532 }
533
534 /// G4_IO2
535 pub mod G4_IO2 {
536 /// Offset (13 bits)
537 pub const offset: u32 = 13;
538 /// Mask (1 bit: 1 << 13)
539 pub const mask: u32 = 1 << offset;
540 /// Read-only values (empty)
541 pub mod R {}
542 /// Write-only values (empty)
543 pub mod W {}
544 /// Read-write values (empty)
545 pub mod RW {}
546 }
547
548 /// G4_IO1
549 pub mod G4_IO1 {
550 /// Offset (12 bits)
551 pub const offset: u32 = 12;
552 /// Mask (1 bit: 1 << 12)
553 pub const mask: u32 = 1 << offset;
554 /// Read-only values (empty)
555 pub mod R {}
556 /// Write-only values (empty)
557 pub mod W {}
558 /// Read-write values (empty)
559 pub mod RW {}
560 }
561
562 /// G3_IO4
563 pub mod G3_IO4 {
564 /// Offset (11 bits)
565 pub const offset: u32 = 11;
566 /// Mask (1 bit: 1 << 11)
567 pub const mask: u32 = 1 << offset;
568 /// Read-only values (empty)
569 pub mod R {}
570 /// Write-only values (empty)
571 pub mod W {}
572 /// Read-write values (empty)
573 pub mod RW {}
574 }
575
576 /// G3_IO3
577 pub mod G3_IO3 {
578 /// Offset (10 bits)
579 pub const offset: u32 = 10;
580 /// Mask (1 bit: 1 << 10)
581 pub const mask: u32 = 1 << offset;
582 /// Read-only values (empty)
583 pub mod R {}
584 /// Write-only values (empty)
585 pub mod W {}
586 /// Read-write values (empty)
587 pub mod RW {}
588 }
589
590 /// G3_IO2
591 pub mod G3_IO2 {
592 /// Offset (9 bits)
593 pub const offset: u32 = 9;
594 /// Mask (1 bit: 1 << 9)
595 pub const mask: u32 = 1 << offset;
596 /// Read-only values (empty)
597 pub mod R {}
598 /// Write-only values (empty)
599 pub mod W {}
600 /// Read-write values (empty)
601 pub mod RW {}
602 }
603
604 /// G3_IO1
605 pub mod G3_IO1 {
606 /// Offset (8 bits)
607 pub const offset: u32 = 8;
608 /// Mask (1 bit: 1 << 8)
609 pub const mask: u32 = 1 << offset;
610 /// Read-only values (empty)
611 pub mod R {}
612 /// Write-only values (empty)
613 pub mod W {}
614 /// Read-write values (empty)
615 pub mod RW {}
616 }
617
618 /// G2_IO4
619 pub mod G2_IO4 {
620 /// Offset (7 bits)
621 pub const offset: u32 = 7;
622 /// Mask (1 bit: 1 << 7)
623 pub const mask: u32 = 1 << offset;
624 /// Read-only values (empty)
625 pub mod R {}
626 /// Write-only values (empty)
627 pub mod W {}
628 /// Read-write values (empty)
629 pub mod RW {}
630 }
631
632 /// G2_IO3
633 pub mod G2_IO3 {
634 /// Offset (6 bits)
635 pub const offset: u32 = 6;
636 /// Mask (1 bit: 1 << 6)
637 pub const mask: u32 = 1 << offset;
638 /// Read-only values (empty)
639 pub mod R {}
640 /// Write-only values (empty)
641 pub mod W {}
642 /// Read-write values (empty)
643 pub mod RW {}
644 }
645
646 /// G2_IO2
647 pub mod G2_IO2 {
648 /// Offset (5 bits)
649 pub const offset: u32 = 5;
650 /// Mask (1 bit: 1 << 5)
651 pub const mask: u32 = 1 << offset;
652 /// Read-only values (empty)
653 pub mod R {}
654 /// Write-only values (empty)
655 pub mod W {}
656 /// Read-write values (empty)
657 pub mod RW {}
658 }
659
660 /// G2_IO1
661 pub mod G2_IO1 {
662 /// Offset (4 bits)
663 pub const offset: u32 = 4;
664 /// Mask (1 bit: 1 << 4)
665 pub const mask: u32 = 1 << offset;
666 /// Read-only values (empty)
667 pub mod R {}
668 /// Write-only values (empty)
669 pub mod W {}
670 /// Read-write values (empty)
671 pub mod RW {}
672 }
673
674 /// G1_IO4
675 pub mod G1_IO4 {
676 /// Offset (3 bits)
677 pub const offset: u32 = 3;
678 /// Mask (1 bit: 1 << 3)
679 pub const mask: u32 = 1 << offset;
680 /// Read-only values (empty)
681 pub mod R {}
682 /// Write-only values (empty)
683 pub mod W {}
684 /// Read-write values (empty)
685 pub mod RW {}
686 }
687
688 /// G1_IO3
689 pub mod G1_IO3 {
690 /// Offset (2 bits)
691 pub const offset: u32 = 2;
692 /// Mask (1 bit: 1 << 2)
693 pub const mask: u32 = 1 << offset;
694 /// Read-only values (empty)
695 pub mod R {}
696 /// Write-only values (empty)
697 pub mod W {}
698 /// Read-write values (empty)
699 pub mod RW {}
700 }
701
702 /// G1_IO2
703 pub mod G1_IO2 {
704 /// Offset (1 bits)
705 pub const offset: u32 = 1;
706 /// Mask (1 bit: 1 << 1)
707 pub const mask: u32 = 1 << offset;
708 /// Read-only values (empty)
709 pub mod R {}
710 /// Write-only values (empty)
711 pub mod W {}
712 /// Read-write values (empty)
713 pub mod RW {}
714 }
715
716 /// G1_IO1
717 pub mod G1_IO1 {
718 /// Offset (0 bits)
719 pub const offset: u32 = 0;
720 /// Mask (1 bit: 1 << 0)
721 pub const mask: u32 = 1 << offset;
722 /// Read-only values (empty)
723 pub mod R {}
724 /// Write-only values (empty)
725 pub mod W {}
726 /// Read-write values (empty)
727 pub mod RW {}
728 }
729}
730
731/// I/O analog switch control register
732pub mod IOASCR {
733 pub use super::IOHCR::G1_IO1;
734 pub use super::IOHCR::G1_IO2;
735 pub use super::IOHCR::G1_IO3;
736 pub use super::IOHCR::G1_IO4;
737 pub use super::IOHCR::G2_IO1;
738 pub use super::IOHCR::G2_IO2;
739 pub use super::IOHCR::G2_IO3;
740 pub use super::IOHCR::G2_IO4;
741 pub use super::IOHCR::G3_IO1;
742 pub use super::IOHCR::G3_IO2;
743 pub use super::IOHCR::G3_IO3;
744 pub use super::IOHCR::G3_IO4;
745 pub use super::IOHCR::G4_IO1;
746 pub use super::IOHCR::G4_IO2;
747 pub use super::IOHCR::G4_IO3;
748 pub use super::IOHCR::G4_IO4;
749 pub use super::IOHCR::G5_IO1;
750 pub use super::IOHCR::G5_IO2;
751 pub use super::IOHCR::G5_IO3;
752 pub use super::IOHCR::G5_IO4;
753 pub use super::IOHCR::G6_IO1;
754 pub use super::IOHCR::G6_IO2;
755 pub use super::IOHCR::G6_IO3;
756 pub use super::IOHCR::G6_IO4;
757 pub use super::IOHCR::G7_IO1;
758 pub use super::IOHCR::G7_IO2;
759 pub use super::IOHCR::G7_IO3;
760 pub use super::IOHCR::G7_IO4;
761 pub use super::IOHCR::G8_IO1;
762 pub use super::IOHCR::G8_IO2;
763 pub use super::IOHCR::G8_IO3;
764 pub use super::IOHCR::G8_IO4;
765}
766
767/// I/O sampling control register
768pub mod IOSCR {
769 pub use super::IOHCR::G1_IO1;
770 pub use super::IOHCR::G1_IO2;
771 pub use super::IOHCR::G1_IO3;
772 pub use super::IOHCR::G1_IO4;
773 pub use super::IOHCR::G2_IO1;
774 pub use super::IOHCR::G2_IO2;
775 pub use super::IOHCR::G2_IO3;
776 pub use super::IOHCR::G2_IO4;
777 pub use super::IOHCR::G3_IO1;
778 pub use super::IOHCR::G3_IO2;
779 pub use super::IOHCR::G3_IO3;
780 pub use super::IOHCR::G3_IO4;
781 pub use super::IOHCR::G4_IO1;
782 pub use super::IOHCR::G4_IO2;
783 pub use super::IOHCR::G4_IO3;
784 pub use super::IOHCR::G4_IO4;
785 pub use super::IOHCR::G5_IO1;
786 pub use super::IOHCR::G5_IO2;
787 pub use super::IOHCR::G5_IO3;
788 pub use super::IOHCR::G5_IO4;
789 pub use super::IOHCR::G6_IO1;
790 pub use super::IOHCR::G6_IO2;
791 pub use super::IOHCR::G6_IO3;
792 pub use super::IOHCR::G6_IO4;
793 pub use super::IOHCR::G7_IO1;
794 pub use super::IOHCR::G7_IO2;
795 pub use super::IOHCR::G7_IO3;
796 pub use super::IOHCR::G7_IO4;
797 pub use super::IOHCR::G8_IO1;
798 pub use super::IOHCR::G8_IO2;
799 pub use super::IOHCR::G8_IO3;
800 pub use super::IOHCR::G8_IO4;
801}
802
803/// I/O channel control register
804pub mod IOCCR {
805 pub use super::IOHCR::G1_IO1;
806 pub use super::IOHCR::G1_IO2;
807 pub use super::IOHCR::G1_IO3;
808 pub use super::IOHCR::G1_IO4;
809 pub use super::IOHCR::G2_IO1;
810 pub use super::IOHCR::G2_IO2;
811 pub use super::IOHCR::G2_IO3;
812 pub use super::IOHCR::G2_IO4;
813 pub use super::IOHCR::G3_IO1;
814 pub use super::IOHCR::G3_IO2;
815 pub use super::IOHCR::G3_IO3;
816 pub use super::IOHCR::G3_IO4;
817 pub use super::IOHCR::G4_IO1;
818 pub use super::IOHCR::G4_IO2;
819 pub use super::IOHCR::G4_IO3;
820 pub use super::IOHCR::G4_IO4;
821 pub use super::IOHCR::G5_IO1;
822 pub use super::IOHCR::G5_IO2;
823 pub use super::IOHCR::G5_IO3;
824 pub use super::IOHCR::G5_IO4;
825 pub use super::IOHCR::G6_IO1;
826 pub use super::IOHCR::G6_IO2;
827 pub use super::IOHCR::G6_IO3;
828 pub use super::IOHCR::G6_IO4;
829 pub use super::IOHCR::G7_IO1;
830 pub use super::IOHCR::G7_IO2;
831 pub use super::IOHCR::G7_IO3;
832 pub use super::IOHCR::G7_IO4;
833 pub use super::IOHCR::G8_IO1;
834 pub use super::IOHCR::G8_IO2;
835 pub use super::IOHCR::G8_IO3;
836 pub use super::IOHCR::G8_IO4;
837}
838
839/// I/O group control status register
840pub mod IOGCSR {
841
842 /// Analog I/O group x status
843 pub mod G8S {
844 /// Offset (23 bits)
845 pub const offset: u32 = 23;
846 /// Mask (1 bit: 1 << 23)
847 pub const mask: u32 = 1 << offset;
848 /// Read-only values (empty)
849 pub mod R {}
850 /// Write-only values (empty)
851 pub mod W {}
852 /// Read-write values (empty)
853 pub mod RW {}
854 }
855
856 /// Analog I/O group x status
857 pub mod G7S {
858 /// Offset (22 bits)
859 pub const offset: u32 = 22;
860 /// Mask (1 bit: 1 << 22)
861 pub const mask: u32 = 1 << offset;
862 /// Read-only values (empty)
863 pub mod R {}
864 /// Write-only values (empty)
865 pub mod W {}
866 /// Read-write values (empty)
867 pub mod RW {}
868 }
869
870 /// Analog I/O group x status
871 pub mod G6S {
872 /// Offset (21 bits)
873 pub const offset: u32 = 21;
874 /// Mask (1 bit: 1 << 21)
875 pub const mask: u32 = 1 << offset;
876 /// Read-only values (empty)
877 pub mod R {}
878 /// Write-only values (empty)
879 pub mod W {}
880 /// Read-write values (empty)
881 pub mod RW {}
882 }
883
884 /// Analog I/O group x status
885 pub mod G5S {
886 /// Offset (20 bits)
887 pub const offset: u32 = 20;
888 /// Mask (1 bit: 1 << 20)
889 pub const mask: u32 = 1 << offset;
890 /// Read-only values (empty)
891 pub mod R {}
892 /// Write-only values (empty)
893 pub mod W {}
894 /// Read-write values (empty)
895 pub mod RW {}
896 }
897
898 /// Analog I/O group x status
899 pub mod G4S {
900 /// Offset (19 bits)
901 pub const offset: u32 = 19;
902 /// Mask (1 bit: 1 << 19)
903 pub const mask: u32 = 1 << offset;
904 /// Read-only values (empty)
905 pub mod R {}
906 /// Write-only values (empty)
907 pub mod W {}
908 /// Read-write values (empty)
909 pub mod RW {}
910 }
911
912 /// Analog I/O group x status
913 pub mod G3S {
914 /// Offset (18 bits)
915 pub const offset: u32 = 18;
916 /// Mask (1 bit: 1 << 18)
917 pub const mask: u32 = 1 << offset;
918 /// Read-only values (empty)
919 pub mod R {}
920 /// Write-only values (empty)
921 pub mod W {}
922 /// Read-write values (empty)
923 pub mod RW {}
924 }
925
926 /// Analog I/O group x status
927 pub mod G2S {
928 /// Offset (17 bits)
929 pub const offset: u32 = 17;
930 /// Mask (1 bit: 1 << 17)
931 pub const mask: u32 = 1 << offset;
932 /// Read-only values (empty)
933 pub mod R {}
934 /// Write-only values (empty)
935 pub mod W {}
936 /// Read-write values (empty)
937 pub mod RW {}
938 }
939
940 /// Analog I/O group x status
941 pub mod G1S {
942 /// Offset (16 bits)
943 pub const offset: u32 = 16;
944 /// Mask (1 bit: 1 << 16)
945 pub const mask: u32 = 1 << offset;
946 /// Read-only values (empty)
947 pub mod R {}
948 /// Write-only values (empty)
949 pub mod W {}
950 /// Read-write values (empty)
951 pub mod RW {}
952 }
953
954 /// Analog I/O group x enable
955 pub mod G8E {
956 /// Offset (7 bits)
957 pub const offset: u32 = 7;
958 /// Mask (1 bit: 1 << 7)
959 pub const mask: u32 = 1 << offset;
960 /// Read-only values (empty)
961 pub mod R {}
962 /// Write-only values (empty)
963 pub mod W {}
964 /// Read-write values (empty)
965 pub mod RW {}
966 }
967
968 /// Analog I/O group x enable
969 pub mod G7E {
970 /// Offset (6 bits)
971 pub const offset: u32 = 6;
972 /// Mask (1 bit: 1 << 6)
973 pub const mask: u32 = 1 << offset;
974 /// Read-only values (empty)
975 pub mod R {}
976 /// Write-only values (empty)
977 pub mod W {}
978 /// Read-write values (empty)
979 pub mod RW {}
980 }
981
982 /// Analog I/O group x enable
983 pub mod G6E {
984 /// Offset (5 bits)
985 pub const offset: u32 = 5;
986 /// Mask (1 bit: 1 << 5)
987 pub const mask: u32 = 1 << offset;
988 /// Read-only values (empty)
989 pub mod R {}
990 /// Write-only values (empty)
991 pub mod W {}
992 /// Read-write values (empty)
993 pub mod RW {}
994 }
995
996 /// Analog I/O group x enable
997 pub mod G5E {
998 /// Offset (4 bits)
999 pub const offset: u32 = 4;
1000 /// Mask (1 bit: 1 << 4)
1001 pub const mask: u32 = 1 << offset;
1002 /// Read-only values (empty)
1003 pub mod R {}
1004 /// Write-only values (empty)
1005 pub mod W {}
1006 /// Read-write values (empty)
1007 pub mod RW {}
1008 }
1009
1010 /// Analog I/O group x enable
1011 pub mod G4E {
1012 /// Offset (3 bits)
1013 pub const offset: u32 = 3;
1014 /// Mask (1 bit: 1 << 3)
1015 pub const mask: u32 = 1 << offset;
1016 /// Read-only values (empty)
1017 pub mod R {}
1018 /// Write-only values (empty)
1019 pub mod W {}
1020 /// Read-write values (empty)
1021 pub mod RW {}
1022 }
1023
1024 /// Analog I/O group x enable
1025 pub mod G3E {
1026 /// Offset (2 bits)
1027 pub const offset: u32 = 2;
1028 /// Mask (1 bit: 1 << 2)
1029 pub const mask: u32 = 1 << offset;
1030 /// Read-only values (empty)
1031 pub mod R {}
1032 /// Write-only values (empty)
1033 pub mod W {}
1034 /// Read-write values (empty)
1035 pub mod RW {}
1036 }
1037
1038 /// Analog I/O group x enable
1039 pub mod G2E {
1040 /// Offset (1 bits)
1041 pub const offset: u32 = 1;
1042 /// Mask (1 bit: 1 << 1)
1043 pub const mask: u32 = 1 << offset;
1044 /// Read-only values (empty)
1045 pub mod R {}
1046 /// Write-only values (empty)
1047 pub mod W {}
1048 /// Read-write values (empty)
1049 pub mod RW {}
1050 }
1051
1052 /// Analog I/O group x enable
1053 pub mod G1E {
1054 /// Offset (0 bits)
1055 pub const offset: u32 = 0;
1056 /// Mask (1 bit: 1 << 0)
1057 pub const mask: u32 = 1 << offset;
1058 /// Read-only values (empty)
1059 pub mod R {}
1060 /// Write-only values (empty)
1061 pub mod W {}
1062 /// Read-write values (empty)
1063 pub mod RW {}
1064 }
1065}
1066
1067/// I/O group x counter register
1068pub mod IOG1CR {
1069
1070 /// Counter value
1071 pub mod CNT {
1072 /// Offset (0 bits)
1073 pub const offset: u32 = 0;
1074 /// Mask (14 bits: 0x3fff << 0)
1075 pub const mask: u32 = 0x3fff << offset;
1076 /// Read-only values (empty)
1077 pub mod R {}
1078 /// Write-only values (empty)
1079 pub mod W {}
1080 /// Read-write values (empty)
1081 pub mod RW {}
1082 }
1083}
1084
1085/// I/O group x counter register
1086pub mod IOG2CR {
1087 pub use super::IOG1CR::CNT;
1088}
1089
1090/// I/O group x counter register
1091pub mod IOG3CR {
1092 pub use super::IOG1CR::CNT;
1093}
1094
1095/// I/O group x counter register
1096pub mod IOG4CR {
1097 pub use super::IOG1CR::CNT;
1098}
1099
1100/// I/O group x counter register
1101pub mod IOG5CR {
1102 pub use super::IOG1CR::CNT;
1103}
1104
1105/// I/O group x counter register
1106pub mod IOG6CR {
1107 pub use super::IOG1CR::CNT;
1108}
1109
1110/// I/O group x counter register
1111pub mod IOG7CR {
1112 pub use super::IOG1CR::CNT;
1113}
1114
1115/// I/O group x counter register
1116pub mod IOG8CR {
1117 pub use super::IOG1CR::CNT;
1118}
1119#[repr(C)]
1120pub struct RegisterBlock {
1121 /// control register
1122 pub CR: RWRegister<u32>,
1123
1124 /// interrupt enable register
1125 pub IER: RWRegister<u32>,
1126
1127 /// interrupt clear register
1128 pub ICR: RWRegister<u32>,
1129
1130 /// interrupt status register
1131 pub ISR: RWRegister<u32>,
1132
1133 /// I/O hysteresis control register
1134 pub IOHCR: RWRegister<u32>,
1135
1136 _reserved1: [u8; 4],
1137
1138 /// I/O analog switch control register
1139 pub IOASCR: RWRegister<u32>,
1140
1141 _reserved2: [u8; 4],
1142
1143 /// I/O sampling control register
1144 pub IOSCR: RWRegister<u32>,
1145
1146 _reserved3: [u8; 4],
1147
1148 /// I/O channel control register
1149 pub IOCCR: RWRegister<u32>,
1150
1151 _reserved4: [u8; 4],
1152
1153 /// I/O group control status register
1154 pub IOGCSR: RWRegister<u32>,
1155
1156 /// I/O group x counter register
1157 pub IOG1CR: RORegister<u32>,
1158
1159 /// I/O group x counter register
1160 pub IOG2CR: RORegister<u32>,
1161
1162 /// I/O group x counter register
1163 pub IOG3CR: RORegister<u32>,
1164
1165 /// I/O group x counter register
1166 pub IOG4CR: RORegister<u32>,
1167
1168 /// I/O group x counter register
1169 pub IOG5CR: RORegister<u32>,
1170
1171 /// I/O group x counter register
1172 pub IOG6CR: RORegister<u32>,
1173
1174 /// I/O group x counter register
1175 pub IOG7CR: RORegister<u32>,
1176
1177 /// I/O group x counter register
1178 pub IOG8CR: RORegister<u32>,
1179}
1180pub struct ResetValues {
1181 pub CR: u32,
1182 pub IER: u32,
1183 pub ICR: u32,
1184 pub ISR: u32,
1185 pub IOHCR: u32,
1186 pub IOASCR: u32,
1187 pub IOSCR: u32,
1188 pub IOCCR: u32,
1189 pub IOGCSR: u32,
1190 pub IOG1CR: u32,
1191 pub IOG2CR: u32,
1192 pub IOG3CR: u32,
1193 pub IOG4CR: u32,
1194 pub IOG5CR: u32,
1195 pub IOG6CR: u32,
1196 pub IOG7CR: u32,
1197 pub IOG8CR: u32,
1198}
1199#[cfg(not(feature = "nosync"))]
1200pub struct Instance {
1201 pub(crate) addr: u32,
1202 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1203}
1204#[cfg(not(feature = "nosync"))]
1205impl ::core::ops::Deref for Instance {
1206 type Target = RegisterBlock;
1207 #[inline(always)]
1208 fn deref(&self) -> &RegisterBlock {
1209 unsafe { &*(self.addr as *const _) }
1210 }
1211}
1212#[cfg(feature = "rtic")]
1213unsafe impl Send for Instance {}