stm32ral/stm32l0/stm32l0x1/
interrupts.rs

1#[cfg(feature = "rt")]
2extern "C" {
3    fn WWDG();
4    fn PVD();
5    fn RTC();
6    fn FLASH();
7    fn RCC();
8    fn EXTI0_1();
9    fn EXTI2_3();
10    fn EXTI4_15();
11    fn DMA1_Channel1();
12    fn DMA1_Channel2_3();
13    fn DMA1_Channel4_7();
14    fn ADC_COMP();
15    fn LPTIM1();
16    fn USART4_USART5();
17    fn TIM2();
18    fn TIM3();
19    fn TIM6();
20    fn TIM7();
21    fn TIM21();
22    fn I2C3();
23    fn TIM22();
24    fn I2C1();
25    fn I2C2();
26    fn SPI1();
27    fn SPI2();
28    fn USART1();
29    fn USART2();
30    fn AES_RNG_LPUART1();
31}
32
33#[doc(hidden)]
34pub union Vector {
35    _handler: unsafe extern "C" fn(),
36    _reserved: u32,
37}
38
39#[cfg(feature = "rt")]
40#[doc(hidden)]
41#[link_section = ".vector_table.interrupts"]
42#[no_mangle]
43pub static __INTERRUPTS: [Vector; 30] = [
44    Vector { _handler: WWDG },
45    Vector { _handler: PVD },
46    Vector { _handler: RTC },
47    Vector { _handler: FLASH },
48    Vector { _handler: RCC },
49    Vector { _handler: EXTI0_1 },
50    Vector { _handler: EXTI2_3 },
51    Vector { _handler: EXTI4_15 },
52    Vector { _reserved: 0 },
53    Vector {
54        _handler: DMA1_Channel1,
55    },
56    Vector {
57        _handler: DMA1_Channel2_3,
58    },
59    Vector {
60        _handler: DMA1_Channel4_7,
61    },
62    Vector { _handler: ADC_COMP },
63    Vector { _handler: LPTIM1 },
64    Vector {
65        _handler: USART4_USART5,
66    },
67    Vector { _handler: TIM2 },
68    Vector { _handler: TIM3 },
69    Vector { _handler: TIM6 },
70    Vector { _handler: TIM7 },
71    Vector { _reserved: 0 },
72    Vector { _handler: TIM21 },
73    Vector { _handler: I2C3 },
74    Vector { _handler: TIM22 },
75    Vector { _handler: I2C1 },
76    Vector { _handler: I2C2 },
77    Vector { _handler: SPI1 },
78    Vector { _handler: SPI2 },
79    Vector { _handler: USART1 },
80    Vector { _handler: USART2 },
81    Vector {
82        _handler: AES_RNG_LPUART1,
83    },
84];
85
86/// Available interrupts for this device
87#[repr(u16)]
88#[derive(Copy, Clone, Debug, PartialEq, Eq)]
89#[allow(non_camel_case_types)]
90pub enum Interrupt {
91    /// 0: Window Watchdog interrupt
92    WWDG = 0,
93    /// 1: PVD through EXTI line detection
94    PVD = 1,
95    /// 2: RTC global interrupt
96    RTC = 2,
97    /// 3: Flash global interrupt
98    FLASH = 3,
99    /// 4: RCC global interrupt
100    RCC = 4,
101    /// 5: EXTI Line\[1:0\] interrupts
102    EXTI0_1 = 5,
103    /// 6: EXTI Line\[3:2\] interrupts
104    EXTI2_3 = 6,
105    /// 7: EXTI Line15 and EXTI4 interrupts
106    EXTI4_15 = 7,
107    /// 9: DMA1 Channel1 global interrupt
108    DMA1_Channel1 = 9,
109    /// 10: DMA1 Channel2 and 3 interrupts
110    DMA1_Channel2_3 = 10,
111    /// 11: DMA1 Channel4 to 7 interrupts
112    DMA1_Channel4_7 = 11,
113    /// 12: ADC and comparator 1 and 2
114    ADC_COMP = 12,
115    /// 13: LPTIMER1 interrupt through EXTI29
116    LPTIM1 = 13,
117    /// 14: USART4/USART5 global interrupt
118    USART4_USART5 = 14,
119    /// 15: TIM2 global interrupt
120    TIM2 = 15,
121    /// 16: TIM3 global interrupt
122    TIM3 = 16,
123    /// 17: TIM6 global interrupt and DAC
124    TIM6 = 17,
125    /// 18: TIM7 global interrupt and DAC
126    TIM7 = 18,
127    /// 20: TIMER21 global interrupt
128    TIM21 = 20,
129    /// 21: I2C3 global interrupt
130    I2C3 = 21,
131    /// 22: TIMER22 global interrupt
132    TIM22 = 22,
133    /// 23: I2C1 global interrupt
134    I2C1 = 23,
135    /// 24: I2C2 global interrupt
136    I2C2 = 24,
137    /// 25: SPI1_global_interrupt
138    SPI1 = 25,
139    /// 26: SPI2 global interrupt
140    SPI2 = 26,
141    /// 27: USART1 global interrupt
142    USART1 = 27,
143    /// 28: USART2 global interrupt
144    USART2 = 28,
145    /// 29: AES global interrupt RNG global interrupt and LPUART1 global interrupt through
146    AES_RNG_LPUART1 = 29,
147}
148unsafe impl external_cortex_m::interrupt::InterruptNumber for Interrupt {
149    #[inline(always)]
150    fn number(self) -> u16 {
151        self as u16
152    }
153}
stm32ral/stm32l0/stm32l0x1/interrupts.rs

stm32ral/stm32l0/stm32l0x1/
interrupts.rs
