stm32ral/stm32g4/instances/
nvic_stir.rs

1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Nested vectored interrupt controller
4//!
5//! Used by: stm32g431, stm32g441, stm32g471, stm32g473, stm32g474, stm32g483, stm32g484, stm32g491, stm32g4a1
6
7#[cfg(not(feature = "nosync"))]
8pub use crate::stm32g4::peripherals::nvic_stir::Instance;
9pub use crate::stm32g4::peripherals::nvic_stir::STIR;
10pub use crate::stm32g4::peripherals::nvic_stir::{RegisterBlock, ResetValues};
11
12/// Access functions for the NVIC_STIR peripheral instance
13pub mod NVIC_STIR {
14    use super::ResetValues;
15
16    #[cfg(not(feature = "nosync"))]
17    use super::Instance;
18
19    #[cfg(not(feature = "nosync"))]
20    const INSTANCE: Instance = Instance {
21        addr: 0xe000ef00,
22        _marker: ::core::marker::PhantomData,
23    };
24
25    /// Reset values for each field in NVIC_STIR
26    pub const reset: ResetValues = ResetValues { STIR: 0x00000000 };
27
28    #[cfg(not(feature = "nosync"))]
29    #[allow(renamed_and_removed_lints)]
30    #[allow(private_no_mangle_statics)]
31    #[no_mangle]
32    static mut NVIC_STIR_TAKEN: bool = false;
33
34    /// Safe access to NVIC_STIR
35    ///
36    /// This function returns `Some(Instance)` if this instance is not
37    /// currently taken, and `None` if it is. This ensures that if you
38    /// do get `Some(Instance)`, you are ensured unique access to
39    /// the peripheral and there cannot be data races (unless other
40    /// code uses `unsafe`, of course). You can then pass the
41    /// `Instance` around to other functions as required. When you're
42    /// done with it, you can call `release(instance)` to return it.
43    ///
44    /// `Instance` itself dereferences to a `RegisterBlock`, which
45    /// provides access to the peripheral's registers.
46    #[cfg(not(feature = "nosync"))]
47    #[inline]
48    pub fn take() -> Option<Instance> {
49        external_cortex_m::interrupt::free(|_| unsafe {
50            if NVIC_STIR_TAKEN {
51                None
52            } else {
53                NVIC_STIR_TAKEN = true;
54                Some(INSTANCE)
55            }
56        })
57    }
58
59    /// Release exclusive access to NVIC_STIR
60    ///
61    /// This function allows you to return an `Instance` so that it
62    /// is available to `take()` again. This function will panic if
63    /// you return a different `Instance` or if this instance is not
64    /// already taken.
65    #[cfg(not(feature = "nosync"))]
66    #[inline]
67    pub fn release(inst: Instance) {
68        external_cortex_m::interrupt::free(|_| unsafe {
69            if NVIC_STIR_TAKEN && inst.addr == INSTANCE.addr {
70                NVIC_STIR_TAKEN = false;
71            } else {
72                panic!("Released a peripheral which was not taken");
73            }
74        });
75    }
76
77    /// Unsafely steal NVIC_STIR
78    ///
79    /// This function is similar to take() but forcibly takes the
80    /// Instance, marking it as taken irregardless of its previous
81    /// state.
82    #[cfg(not(feature = "nosync"))]
83    #[inline]
84    pub unsafe fn steal() -> Instance {
85        NVIC_STIR_TAKEN = true;
86        INSTANCE
87    }
88}
89
90/// Raw pointer to NVIC_STIR
91///
92/// Dereferencing this is unsafe because you are not ensured unique
93/// access to the peripheral, so you may encounter data races with
94/// other users of this peripheral. It is up to you to ensure you
95/// will not cause data races.
96///
97/// This constant is provided for ease of use in unsafe code: you can
98/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
99pub const NVIC_STIR: *const RegisterBlock = 0xe000ef00 as *const _;
stm32ral/stm32g4/instances/nvic_stir.rs

stm32ral/stm32g4/instances/
nvic_stir.rs
