stm32ral/stm32f7/peripherals/spi.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Serial peripheral interface
4//!
5//! Used by: stm32f730, stm32f745, stm32f750, stm32f765, stm32f7x2, stm32f7x3, stm32f7x6, stm32f7x7, stm32f7x9
6
7use crate::{RORegister, RWRegister};
8#[cfg(not(feature = "nosync"))]
9use core::marker::PhantomData;
10
11/// control register 1
12pub mod CR1 {
13
14 /// Bidirectional data mode enable
15 pub mod BIDIMODE {
16 /// Offset (15 bits)
17 pub const offset: u32 = 15;
18 /// Mask (1 bit: 1 << 15)
19 pub const mask: u32 = 1 << offset;
20 /// Read-only values (empty)
21 pub mod R {}
22 /// Write-only values (empty)
23 pub mod W {}
24 /// Read-write values
25 pub mod RW {
26
27 /// 0b0: 2-line unidirectional data mode selected
28 pub const Unidirectional: u32 = 0b0;
29
30 /// 0b1: 1-line bidirectional data mode selected
31 pub const Bidirectional: u32 = 0b1;
32 }
33 }
34
35 /// Output enable in bidirectional mode
36 pub mod BIDIOE {
37 /// Offset (14 bits)
38 pub const offset: u32 = 14;
39 /// Mask (1 bit: 1 << 14)
40 pub const mask: u32 = 1 << offset;
41 /// Read-only values (empty)
42 pub mod R {}
43 /// Write-only values (empty)
44 pub mod W {}
45 /// Read-write values
46 pub mod RW {
47
48 /// 0b0: Output disabled (receive-only mode)
49 pub const OutputDisabled: u32 = 0b0;
50
51 /// 0b1: Output enabled (transmit-only mode)
52 pub const OutputEnabled: u32 = 0b1;
53 }
54 }
55
56 /// Hardware CRC calculation enable
57 pub mod CRCEN {
58 /// Offset (13 bits)
59 pub const offset: u32 = 13;
60 /// Mask (1 bit: 1 << 13)
61 pub const mask: u32 = 1 << offset;
62 /// Read-only values (empty)
63 pub mod R {}
64 /// Write-only values (empty)
65 pub mod W {}
66 /// Read-write values
67 pub mod RW {
68
69 /// 0b0: CRC calculation disabled
70 pub const Disabled: u32 = 0b0;
71
72 /// 0b1: CRC calculation enabled
73 pub const Enabled: u32 = 0b1;
74 }
75 }
76
77 /// CRC transfer next
78 pub mod CRCNEXT {
79 /// Offset (12 bits)
80 pub const offset: u32 = 12;
81 /// Mask (1 bit: 1 << 12)
82 pub const mask: u32 = 1 << offset;
83 /// Read-only values (empty)
84 pub mod R {}
85 /// Write-only values (empty)
86 pub mod W {}
87 /// Read-write values
88 pub mod RW {
89
90 /// 0b0: Next transmit value is from Tx buffer
91 pub const TxBuffer: u32 = 0b0;
92
93 /// 0b1: Next transmit value is from Tx CRC register
94 pub const CRC: u32 = 0b1;
95 }
96 }
97
98 /// CRC length
99 pub mod CRCL {
100 /// Offset (11 bits)
101 pub const offset: u32 = 11;
102 /// Mask (1 bit: 1 << 11)
103 pub const mask: u32 = 1 << offset;
104 /// Read-only values (empty)
105 pub mod R {}
106 /// Write-only values (empty)
107 pub mod W {}
108 /// Read-write values
109 pub mod RW {
110
111 /// 0b0: 8-bit CRC length
112 pub const EightBit: u32 = 0b0;
113
114 /// 0b1: 16-bit CRC length
115 pub const SixteenBit: u32 = 0b1;
116 }
117 }
118
119 /// Receive only
120 pub mod RXONLY {
121 /// Offset (10 bits)
122 pub const offset: u32 = 10;
123 /// Mask (1 bit: 1 << 10)
124 pub const mask: u32 = 1 << offset;
125 /// Read-only values (empty)
126 pub mod R {}
127 /// Write-only values (empty)
128 pub mod W {}
129 /// Read-write values
130 pub mod RW {
131
132 /// 0b0: Full duplex (Transmit and receive)
133 pub const FullDuplex: u32 = 0b0;
134
135 /// 0b1: Output disabled (Receive-only mode)
136 pub const OutputDisabled: u32 = 0b1;
137 }
138 }
139
140 /// Software slave management
141 pub mod SSM {
142 /// Offset (9 bits)
143 pub const offset: u32 = 9;
144 /// Mask (1 bit: 1 << 9)
145 pub const mask: u32 = 1 << offset;
146 /// Read-only values (empty)
147 pub mod R {}
148 /// Write-only values (empty)
149 pub mod W {}
150 /// Read-write values
151 pub mod RW {
152
153 /// 0b0: Software slave management disabled
154 pub const Disabled: u32 = 0b0;
155
156 /// 0b1: Software slave management enabled
157 pub const Enabled: u32 = 0b1;
158 }
159 }
160
161 /// Internal slave select
162 pub mod SSI {
163 /// Offset (8 bits)
164 pub const offset: u32 = 8;
165 /// Mask (1 bit: 1 << 8)
166 pub const mask: u32 = 1 << offset;
167 /// Read-only values (empty)
168 pub mod R {}
169 /// Write-only values (empty)
170 pub mod W {}
171 /// Read-write values
172 pub mod RW {
173
174 /// 0b0: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
175 pub const SlaveSelected: u32 = 0b0;
176
177 /// 0b1: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
178 pub const SlaveNotSelected: u32 = 0b1;
179 }
180 }
181
182 /// Frame format
183 pub mod LSBFIRST {
184 /// Offset (7 bits)
185 pub const offset: u32 = 7;
186 /// Mask (1 bit: 1 << 7)
187 pub const mask: u32 = 1 << offset;
188 /// Read-only values (empty)
189 pub mod R {}
190 /// Write-only values (empty)
191 pub mod W {}
192 /// Read-write values
193 pub mod RW {
194
195 /// 0b0: Data is transmitted/received with the MSB first
196 pub const MSBFirst: u32 = 0b0;
197
198 /// 0b1: Data is transmitted/received with the LSB first
199 pub const LSBFirst: u32 = 0b1;
200 }
201 }
202
203 /// SPI enable
204 pub mod SPE {
205 /// Offset (6 bits)
206 pub const offset: u32 = 6;
207 /// Mask (1 bit: 1 << 6)
208 pub const mask: u32 = 1 << offset;
209 /// Read-only values (empty)
210 pub mod R {}
211 /// Write-only values (empty)
212 pub mod W {}
213 /// Read-write values
214 pub mod RW {
215
216 /// 0b0: Peripheral disabled
217 pub const Disabled: u32 = 0b0;
218
219 /// 0b1: Peripheral enabled
220 pub const Enabled: u32 = 0b1;
221 }
222 }
223
224 /// Baud rate control
225 pub mod BR {
226 /// Offset (3 bits)
227 pub const offset: u32 = 3;
228 /// Mask (3 bits: 0b111 << 3)
229 pub const mask: u32 = 0b111 << offset;
230 /// Read-only values (empty)
231 pub mod R {}
232 /// Write-only values (empty)
233 pub mod W {}
234 /// Read-write values
235 pub mod RW {
236
237 /// 0b000: f_PCLK / 2
238 pub const Div2: u32 = 0b000;
239
240 /// 0b001: f_PCLK / 4
241 pub const Div4: u32 = 0b001;
242
243 /// 0b010: f_PCLK / 8
244 pub const Div8: u32 = 0b010;
245
246 /// 0b011: f_PCLK / 16
247 pub const Div16: u32 = 0b011;
248
249 /// 0b100: f_PCLK / 32
250 pub const Div32: u32 = 0b100;
251
252 /// 0b101: f_PCLK / 64
253 pub const Div64: u32 = 0b101;
254
255 /// 0b110: f_PCLK / 128
256 pub const Div128: u32 = 0b110;
257
258 /// 0b111: f_PCLK / 256
259 pub const Div256: u32 = 0b111;
260 }
261 }
262
263 /// Master selection
264 pub mod MSTR {
265 /// Offset (2 bits)
266 pub const offset: u32 = 2;
267 /// Mask (1 bit: 1 << 2)
268 pub const mask: u32 = 1 << offset;
269 /// Read-only values (empty)
270 pub mod R {}
271 /// Write-only values (empty)
272 pub mod W {}
273 /// Read-write values
274 pub mod RW {
275
276 /// 0b0: Slave configuration
277 pub const Slave: u32 = 0b0;
278
279 /// 0b1: Master configuration
280 pub const Master: u32 = 0b1;
281 }
282 }
283
284 /// Clock polarity
285 pub mod CPOL {
286 /// Offset (1 bits)
287 pub const offset: u32 = 1;
288 /// Mask (1 bit: 1 << 1)
289 pub const mask: u32 = 1 << offset;
290 /// Read-only values (empty)
291 pub mod R {}
292 /// Write-only values (empty)
293 pub mod W {}
294 /// Read-write values
295 pub mod RW {
296
297 /// 0b0: CK to 0 when idle
298 pub const IdleLow: u32 = 0b0;
299
300 /// 0b1: CK to 1 when idle
301 pub const IdleHigh: u32 = 0b1;
302 }
303 }
304
305 /// Clock phase
306 pub mod CPHA {
307 /// Offset (0 bits)
308 pub const offset: u32 = 0;
309 /// Mask (1 bit: 1 << 0)
310 pub const mask: u32 = 1 << offset;
311 /// Read-only values (empty)
312 pub mod R {}
313 /// Write-only values (empty)
314 pub mod W {}
315 /// Read-write values
316 pub mod RW {
317
318 /// 0b0: The first clock transition is the first data capture edge
319 pub const FirstEdge: u32 = 0b0;
320
321 /// 0b1: The second clock transition is the first data capture edge
322 pub const SecondEdge: u32 = 0b1;
323 }
324 }
325}
326
327/// control register 2
328pub mod CR2 {
329
330 /// Rx buffer DMA enable
331 pub mod RXDMAEN {
332 /// Offset (0 bits)
333 pub const offset: u32 = 0;
334 /// Mask (1 bit: 1 << 0)
335 pub const mask: u32 = 1 << offset;
336 /// Read-only values (empty)
337 pub mod R {}
338 /// Write-only values (empty)
339 pub mod W {}
340 /// Read-write values
341 pub mod RW {
342
343 /// 0b0: Rx buffer DMA disabled
344 pub const Disabled: u32 = 0b0;
345
346 /// 0b1: Rx buffer DMA enabled
347 pub const Enabled: u32 = 0b1;
348 }
349 }
350
351 /// Tx buffer DMA enable
352 pub mod TXDMAEN {
353 /// Offset (1 bits)
354 pub const offset: u32 = 1;
355 /// Mask (1 bit: 1 << 1)
356 pub const mask: u32 = 1 << offset;
357 /// Read-only values (empty)
358 pub mod R {}
359 /// Write-only values (empty)
360 pub mod W {}
361 /// Read-write values
362 pub mod RW {
363
364 /// 0b0: Tx buffer DMA disabled
365 pub const Disabled: u32 = 0b0;
366
367 /// 0b1: Tx buffer DMA enabled
368 pub const Enabled: u32 = 0b1;
369 }
370 }
371
372 /// SS output enable
373 pub mod SSOE {
374 /// Offset (2 bits)
375 pub const offset: u32 = 2;
376 /// Mask (1 bit: 1 << 2)
377 pub const mask: u32 = 1 << offset;
378 /// Read-only values (empty)
379 pub mod R {}
380 /// Write-only values (empty)
381 pub mod W {}
382 /// Read-write values
383 pub mod RW {
384
385 /// 0b0: SS output is disabled in master mode
386 pub const Disabled: u32 = 0b0;
387
388 /// 0b1: SS output is enabled in master mode
389 pub const Enabled: u32 = 0b1;
390 }
391 }
392
393 /// NSS pulse management
394 pub mod NSSP {
395 /// Offset (3 bits)
396 pub const offset: u32 = 3;
397 /// Mask (1 bit: 1 << 3)
398 pub const mask: u32 = 1 << offset;
399 /// Read-only values (empty)
400 pub mod R {}
401 /// Write-only values (empty)
402 pub mod W {}
403 /// Read-write values
404 pub mod RW {
405
406 /// 0b0: No NSS pulse
407 pub const NoPulse: u32 = 0b0;
408
409 /// 0b1: NSS pulse generated
410 pub const PulseGenerated: u32 = 0b1;
411 }
412 }
413
414 /// Frame format
415 pub mod FRF {
416 /// Offset (4 bits)
417 pub const offset: u32 = 4;
418 /// Mask (1 bit: 1 << 4)
419 pub const mask: u32 = 1 << offset;
420 /// Read-only values (empty)
421 pub mod R {}
422 /// Write-only values (empty)
423 pub mod W {}
424 /// Read-write values
425 pub mod RW {
426
427 /// 0b0: SPI Motorola mode
428 pub const Motorola: u32 = 0b0;
429
430 /// 0b1: SPI TI mode
431 pub const TI: u32 = 0b1;
432 }
433 }
434
435 /// Error interrupt enable
436 pub mod ERRIE {
437 /// Offset (5 bits)
438 pub const offset: u32 = 5;
439 /// Mask (1 bit: 1 << 5)
440 pub const mask: u32 = 1 << offset;
441 /// Read-only values (empty)
442 pub mod R {}
443 /// Write-only values (empty)
444 pub mod W {}
445 /// Read-write values
446 pub mod RW {
447
448 /// 0b0: Error interrupt masked
449 pub const Masked: u32 = 0b0;
450
451 /// 0b1: Error interrupt not masked
452 pub const NotMasked: u32 = 0b1;
453 }
454 }
455
456 /// RX buffer not empty interrupt enable
457 pub mod RXNEIE {
458 /// Offset (6 bits)
459 pub const offset: u32 = 6;
460 /// Mask (1 bit: 1 << 6)
461 pub const mask: u32 = 1 << offset;
462 /// Read-only values (empty)
463 pub mod R {}
464 /// Write-only values (empty)
465 pub mod W {}
466 /// Read-write values
467 pub mod RW {
468
469 /// 0b0: RXE interrupt masked
470 pub const Masked: u32 = 0b0;
471
472 /// 0b1: RXE interrupt not masked
473 pub const NotMasked: u32 = 0b1;
474 }
475 }
476
477 /// Tx buffer empty interrupt enable
478 pub mod TXEIE {
479 /// Offset (7 bits)
480 pub const offset: u32 = 7;
481 /// Mask (1 bit: 1 << 7)
482 pub const mask: u32 = 1 << offset;
483 /// Read-only values (empty)
484 pub mod R {}
485 /// Write-only values (empty)
486 pub mod W {}
487 /// Read-write values
488 pub mod RW {
489
490 /// 0b0: TXE interrupt masked
491 pub const Masked: u32 = 0b0;
492
493 /// 0b1: TXE interrupt not masked
494 pub const NotMasked: u32 = 0b1;
495 }
496 }
497
498 /// Data size
499 pub mod DS {
500 /// Offset (8 bits)
501 pub const offset: u32 = 8;
502 /// Mask (4 bits: 0b1111 << 8)
503 pub const mask: u32 = 0b1111 << offset;
504 /// Read-only values (empty)
505 pub mod R {}
506 /// Write-only values (empty)
507 pub mod W {}
508 /// Read-write values
509 pub mod RW {
510
511 /// 0b0011: 4-bit
512 pub const FourBit: u32 = 0b0011;
513
514 /// 0b0100: 5-bit
515 pub const FiveBit: u32 = 0b0100;
516
517 /// 0b0101: 6-bit
518 pub const SixBit: u32 = 0b0101;
519
520 /// 0b0110: 7-bit
521 pub const SevenBit: u32 = 0b0110;
522
523 /// 0b0111: 8-bit
524 pub const EightBit: u32 = 0b0111;
525
526 /// 0b1000: 9-bit
527 pub const NineBit: u32 = 0b1000;
528
529 /// 0b1001: 10-bit
530 pub const TenBit: u32 = 0b1001;
531
532 /// 0b1010: 11-bit
533 pub const ElevenBit: u32 = 0b1010;
534
535 /// 0b1011: 12-bit
536 pub const TwelveBit: u32 = 0b1011;
537
538 /// 0b1100: 13-bit
539 pub const ThirteenBit: u32 = 0b1100;
540
541 /// 0b1101: 14-bit
542 pub const FourteenBit: u32 = 0b1101;
543
544 /// 0b1110: 15-bit
545 pub const FifteenBit: u32 = 0b1110;
546
547 /// 0b1111: 16-bit
548 pub const SixteenBit: u32 = 0b1111;
549 }
550 }
551
552 /// FIFO reception threshold
553 pub mod FRXTH {
554 /// Offset (12 bits)
555 pub const offset: u32 = 12;
556 /// Mask (1 bit: 1 << 12)
557 pub const mask: u32 = 1 << offset;
558 /// Read-only values (empty)
559 pub mod R {}
560 /// Write-only values (empty)
561 pub mod W {}
562 /// Read-write values
563 pub mod RW {
564
565 /// 0b0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
566 pub const Half: u32 = 0b0;
567
568 /// 0b1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
569 pub const Quarter: u32 = 0b1;
570 }
571 }
572
573 /// Last DMA transfer for reception
574 pub mod LDMA_RX {
575 /// Offset (13 bits)
576 pub const offset: u32 = 13;
577 /// Mask (1 bit: 1 << 13)
578 pub const mask: u32 = 1 << offset;
579 /// Read-only values (empty)
580 pub mod R {}
581 /// Write-only values (empty)
582 pub mod W {}
583 /// Read-write values
584 pub mod RW {
585
586 /// 0b0: Number of data to transfer for receive is even
587 pub const Even: u32 = 0b0;
588
589 /// 0b1: Number of data to transfer for receive is odd
590 pub const Odd: u32 = 0b1;
591 }
592 }
593
594 /// Last DMA transfer for transmission
595 pub mod LDMA_TX {
596 /// Offset (14 bits)
597 pub const offset: u32 = 14;
598 /// Mask (1 bit: 1 << 14)
599 pub const mask: u32 = 1 << offset;
600 /// Read-only values (empty)
601 pub mod R {}
602 /// Write-only values (empty)
603 pub mod W {}
604 /// Read-write values
605 pub mod RW {
606
607 /// 0b0: Number of data to transfer for transmit is even
608 pub const Even: u32 = 0b0;
609
610 /// 0b1: Number of data to transfer for transmit is odd
611 pub const Odd: u32 = 0b1;
612 }
613 }
614}
615
616/// status register
617pub mod SR {
618
619 /// frame format error
620 pub mod FRE {
621 /// Offset (8 bits)
622 pub const offset: u32 = 8;
623 /// Mask (1 bit: 1 << 8)
624 pub const mask: u32 = 1 << offset;
625 /// Read-only values
626 pub mod R {
627
628 /// 0b0: No frame format error
629 pub const NoError: u32 = 0b0;
630
631 /// 0b1: A frame format error occurred
632 pub const Error: u32 = 0b1;
633 }
634 /// Write-only values (empty)
635 pub mod W {}
636 /// Read-write values (empty)
637 pub mod RW {}
638 }
639
640 /// Busy flag
641 pub mod BSY {
642 /// Offset (7 bits)
643 pub const offset: u32 = 7;
644 /// Mask (1 bit: 1 << 7)
645 pub const mask: u32 = 1 << offset;
646 /// Read-only values
647 pub mod R {
648
649 /// 0b0: SPI not busy
650 pub const NotBusy: u32 = 0b0;
651
652 /// 0b1: SPI busy
653 pub const Busy: u32 = 0b1;
654 }
655 /// Write-only values (empty)
656 pub mod W {}
657 /// Read-write values (empty)
658 pub mod RW {}
659 }
660
661 /// Overrun flag
662 pub mod OVR {
663 /// Offset (6 bits)
664 pub const offset: u32 = 6;
665 /// Mask (1 bit: 1 << 6)
666 pub const mask: u32 = 1 << offset;
667 /// Read-only values
668 pub mod R {
669
670 /// 0b0: No overrun occurred
671 pub const NoOverrun: u32 = 0b0;
672
673 /// 0b1: Overrun occurred
674 pub const Overrun: u32 = 0b1;
675 }
676 /// Write-only values (empty)
677 pub mod W {}
678 /// Read-write values (empty)
679 pub mod RW {}
680 }
681
682 /// Mode fault
683 pub mod MODF {
684 /// Offset (5 bits)
685 pub const offset: u32 = 5;
686 /// Mask (1 bit: 1 << 5)
687 pub const mask: u32 = 1 << offset;
688 /// Read-only values
689 pub mod R {
690
691 /// 0b0: No mode fault occurred
692 pub const NoFault: u32 = 0b0;
693
694 /// 0b1: Mode fault occurred
695 pub const Fault: u32 = 0b1;
696 }
697 /// Write-only values (empty)
698 pub mod W {}
699 /// Read-write values (empty)
700 pub mod RW {}
701 }
702
703 /// CRC error flag
704 pub mod CRCERR {
705 /// Offset (4 bits)
706 pub const offset: u32 = 4;
707 /// Mask (1 bit: 1 << 4)
708 pub const mask: u32 = 1 << offset;
709 /// Read-only values (empty)
710 pub mod R {}
711 /// Write-only values (empty)
712 pub mod W {}
713 /// Read-write values
714 pub mod RW {
715
716 /// 0b0: CRC value received matches the SPIx_RXCRCR value
717 pub const Match: u32 = 0b0;
718
719 /// 0b1: CRC value received does not match the SPIx_RXCRCR value
720 pub const NoMatch: u32 = 0b1;
721 }
722 }
723
724 /// Underrun flag
725 pub mod UDR {
726 /// Offset (3 bits)
727 pub const offset: u32 = 3;
728 /// Mask (1 bit: 1 << 3)
729 pub const mask: u32 = 1 << offset;
730 /// Read-only values
731 pub mod R {
732
733 /// 0b0: No underrun occurred
734 pub const NoUnderrun: u32 = 0b0;
735
736 /// 0b1: Underrun occurred
737 pub const Underrun: u32 = 0b1;
738 }
739 /// Write-only values (empty)
740 pub mod W {}
741 /// Read-write values (empty)
742 pub mod RW {}
743 }
744
745 /// Channel side
746 pub mod CHSIDE {
747 /// Offset (2 bits)
748 pub const offset: u32 = 2;
749 /// Mask (1 bit: 1 << 2)
750 pub const mask: u32 = 1 << offset;
751 /// Read-only values
752 pub mod R {
753
754 /// 0b0: Channel left has to be transmitted or has been received
755 pub const Left: u32 = 0b0;
756
757 /// 0b1: Channel right has to be transmitted or has been received
758 pub const Right: u32 = 0b1;
759 }
760 /// Write-only values (empty)
761 pub mod W {}
762 /// Read-write values (empty)
763 pub mod RW {}
764 }
765
766 /// Transmit buffer empty
767 pub mod TXE {
768 /// Offset (1 bits)
769 pub const offset: u32 = 1;
770 /// Mask (1 bit: 1 << 1)
771 pub const mask: u32 = 1 << offset;
772 /// Read-only values
773 pub mod R {
774
775 /// 0b0: Tx buffer not empty
776 pub const NotEmpty: u32 = 0b0;
777
778 /// 0b1: Tx buffer empty
779 pub const Empty: u32 = 0b1;
780 }
781 /// Write-only values (empty)
782 pub mod W {}
783 /// Read-write values (empty)
784 pub mod RW {}
785 }
786
787 /// Receive buffer not empty
788 pub mod RXNE {
789 /// Offset (0 bits)
790 pub const offset: u32 = 0;
791 /// Mask (1 bit: 1 << 0)
792 pub const mask: u32 = 1 << offset;
793 /// Read-only values
794 pub mod R {
795
796 /// 0b0: Rx buffer empty
797 pub const Empty: u32 = 0b0;
798
799 /// 0b1: Rx buffer not empty
800 pub const NotEmpty: u32 = 0b1;
801 }
802 /// Write-only values (empty)
803 pub mod W {}
804 /// Read-write values (empty)
805 pub mod RW {}
806 }
807
808 /// FIFO reception level
809 pub mod FRLVL {
810 /// Offset (9 bits)
811 pub const offset: u32 = 9;
812 /// Mask (2 bits: 0b11 << 9)
813 pub const mask: u32 = 0b11 << offset;
814 /// Read-only values
815 pub mod R {
816
817 /// 0b00: Rx FIFO Empty
818 pub const Empty: u32 = 0b00;
819
820 /// 0b01: Rx 1/4 FIFO
821 pub const Quarter: u32 = 0b01;
822
823 /// 0b10: Rx 1/2 FIFO
824 pub const Half: u32 = 0b10;
825
826 /// 0b11: Rx FIFO full
827 pub const Full: u32 = 0b11;
828 }
829 /// Write-only values (empty)
830 pub mod W {}
831 /// Read-write values (empty)
832 pub mod RW {}
833 }
834
835 /// FIFO Transmission Level
836 pub mod FTLVL {
837 /// Offset (11 bits)
838 pub const offset: u32 = 11;
839 /// Mask (2 bits: 0b11 << 11)
840 pub const mask: u32 = 0b11 << offset;
841 /// Read-only values
842 pub mod R {
843
844 /// 0b00: Tx FIFO Empty
845 pub const Empty: u32 = 0b00;
846
847 /// 0b01: Tx 1/4 FIFO
848 pub const Quarter: u32 = 0b01;
849
850 /// 0b10: Tx 1/2 FIFO
851 pub const Half: u32 = 0b10;
852
853 /// 0b11: Tx FIFO full
854 pub const Full: u32 = 0b11;
855 }
856 /// Write-only values (empty)
857 pub mod W {}
858 /// Read-write values (empty)
859 pub mod RW {}
860 }
861}
862
863/// data register
864pub mod DR {
865
866 /// Data register
867 pub mod DR {
868 /// Offset (0 bits)
869 pub const offset: u32 = 0;
870 /// Mask (16 bits: 0xffff << 0)
871 pub const mask: u32 = 0xffff << offset;
872 /// Read-only values (empty)
873 pub mod R {}
874 /// Write-only values (empty)
875 pub mod W {}
876 /// Read-write values (empty)
877 pub mod RW {}
878 }
879}
880
881/// CRC polynomial register
882pub mod CRCPR {
883
884 /// CRC polynomial register
885 pub mod CRCPOLY {
886 /// Offset (0 bits)
887 pub const offset: u32 = 0;
888 /// Mask (16 bits: 0xffff << 0)
889 pub const mask: u32 = 0xffff << offset;
890 /// Read-only values (empty)
891 pub mod R {}
892 /// Write-only values (empty)
893 pub mod W {}
894 /// Read-write values (empty)
895 pub mod RW {}
896 }
897}
898
899/// RX CRC register
900pub mod RXCRCR {
901
902 /// Rx CRC register
903 pub mod RxCRC {
904 /// Offset (0 bits)
905 pub const offset: u32 = 0;
906 /// Mask (16 bits: 0xffff << 0)
907 pub const mask: u32 = 0xffff << offset;
908 /// Read-only values (empty)
909 pub mod R {}
910 /// Write-only values (empty)
911 pub mod W {}
912 /// Read-write values (empty)
913 pub mod RW {}
914 }
915}
916
917/// TX CRC register
918pub mod TXCRCR {
919
920 /// Tx CRC register
921 pub mod TxCRC {
922 /// Offset (0 bits)
923 pub const offset: u32 = 0;
924 /// Mask (16 bits: 0xffff << 0)
925 pub const mask: u32 = 0xffff << offset;
926 /// Read-only values (empty)
927 pub mod R {}
928 /// Write-only values (empty)
929 pub mod W {}
930 /// Read-write values (empty)
931 pub mod RW {}
932 }
933}
934
935/// I2S configuration register
936pub mod I2SCFGR {
937
938 /// I2S mode selection
939 pub mod I2SMOD {
940 /// Offset (11 bits)
941 pub const offset: u32 = 11;
942 /// Mask (1 bit: 1 << 11)
943 pub const mask: u32 = 1 << offset;
944 /// Read-only values (empty)
945 pub mod R {}
946 /// Write-only values (empty)
947 pub mod W {}
948 /// Read-write values
949 pub mod RW {
950
951 /// 0b0: SPI mode is selected
952 pub const SPIMode: u32 = 0b0;
953
954 /// 0b1: I2S mode is selected
955 pub const I2SMode: u32 = 0b1;
956 }
957 }
958
959 /// I2S Enable
960 pub mod I2SE {
961 /// Offset (10 bits)
962 pub const offset: u32 = 10;
963 /// Mask (1 bit: 1 << 10)
964 pub const mask: u32 = 1 << offset;
965 /// Read-only values (empty)
966 pub mod R {}
967 /// Write-only values (empty)
968 pub mod W {}
969 /// Read-write values
970 pub mod RW {
971
972 /// 0b0: I2S peripheral is disabled
973 pub const Disabled: u32 = 0b0;
974
975 /// 0b1: I2S peripheral is enabled
976 pub const Enabled: u32 = 0b1;
977 }
978 }
979
980 /// I2S configuration mode
981 pub mod I2SCFG {
982 /// Offset (8 bits)
983 pub const offset: u32 = 8;
984 /// Mask (2 bits: 0b11 << 8)
985 pub const mask: u32 = 0b11 << offset;
986 /// Read-only values (empty)
987 pub mod R {}
988 /// Write-only values (empty)
989 pub mod W {}
990 /// Read-write values
991 pub mod RW {
992
993 /// 0b00: Slave - transmit
994 pub const SlaveTx: u32 = 0b00;
995
996 /// 0b01: Slave - receive
997 pub const SlaveRx: u32 = 0b01;
998
999 /// 0b10: Master - transmit
1000 pub const MasterTx: u32 = 0b10;
1001
1002 /// 0b11: Master - receive
1003 pub const MasterRx: u32 = 0b11;
1004 }
1005 }
1006
1007 /// PCM frame synchronization
1008 pub mod PCMSYNC {
1009 /// Offset (7 bits)
1010 pub const offset: u32 = 7;
1011 /// Mask (1 bit: 1 << 7)
1012 pub const mask: u32 = 1 << offset;
1013 /// Read-only values (empty)
1014 pub mod R {}
1015 /// Write-only values (empty)
1016 pub mod W {}
1017 /// Read-write values
1018 pub mod RW {
1019
1020 /// 0b0: Short frame synchronisation
1021 pub const Short: u32 = 0b0;
1022
1023 /// 0b1: Long frame synchronisation
1024 pub const Long: u32 = 0b1;
1025 }
1026 }
1027
1028 /// I2S standard selection
1029 pub mod I2SSTD {
1030 /// Offset (4 bits)
1031 pub const offset: u32 = 4;
1032 /// Mask (2 bits: 0b11 << 4)
1033 pub const mask: u32 = 0b11 << offset;
1034 /// Read-only values (empty)
1035 pub mod R {}
1036 /// Write-only values (empty)
1037 pub mod W {}
1038 /// Read-write values
1039 pub mod RW {
1040
1041 /// 0b00: I2S Philips standard
1042 pub const Philips: u32 = 0b00;
1043
1044 /// 0b01: MSB justified standard
1045 pub const MSB: u32 = 0b01;
1046
1047 /// 0b10: LSB justified standard
1048 pub const LSB: u32 = 0b10;
1049
1050 /// 0b11: PCM standard
1051 pub const PCM: u32 = 0b11;
1052 }
1053 }
1054
1055 /// Steady state clock polarity
1056 pub mod CKPOL {
1057 /// Offset (3 bits)
1058 pub const offset: u32 = 3;
1059 /// Mask (1 bit: 1 << 3)
1060 pub const mask: u32 = 1 << offset;
1061 /// Read-only values (empty)
1062 pub mod R {}
1063 /// Write-only values (empty)
1064 pub mod W {}
1065 /// Read-write values
1066 pub mod RW {
1067
1068 /// 0b0: I2S clock inactive state is low level
1069 pub const IdleLow: u32 = 0b0;
1070
1071 /// 0b1: I2S clock inactive state is high level
1072 pub const IdleHigh: u32 = 0b1;
1073 }
1074 }
1075
1076 /// Data length to be transferred
1077 pub mod DATLEN {
1078 /// Offset (1 bits)
1079 pub const offset: u32 = 1;
1080 /// Mask (2 bits: 0b11 << 1)
1081 pub const mask: u32 = 0b11 << offset;
1082 /// Read-only values (empty)
1083 pub mod R {}
1084 /// Write-only values (empty)
1085 pub mod W {}
1086 /// Read-write values
1087 pub mod RW {
1088
1089 /// 0b00: 16-bit data length
1090 pub const SixteenBit: u32 = 0b00;
1091
1092 /// 0b01: 24-bit data length
1093 pub const TwentyFourBit: u32 = 0b01;
1094
1095 /// 0b10: 32-bit data length
1096 pub const ThirtyTwoBit: u32 = 0b10;
1097 }
1098 }
1099
1100 /// Channel length (number of bits per audio channel)
1101 pub mod CHLEN {
1102 /// Offset (0 bits)
1103 pub const offset: u32 = 0;
1104 /// Mask (1 bit: 1 << 0)
1105 pub const mask: u32 = 1 << offset;
1106 /// Read-only values (empty)
1107 pub mod R {}
1108 /// Write-only values (empty)
1109 pub mod W {}
1110 /// Read-write values
1111 pub mod RW {
1112
1113 /// 0b0: 16-bit wide
1114 pub const SixteenBit: u32 = 0b0;
1115
1116 /// 0b1: 32-bit wide
1117 pub const ThirtyTwoBit: u32 = 0b1;
1118 }
1119 }
1120
1121 /// Asynchronous start enable
1122 pub mod ASTRTEN {
1123 /// Offset (12 bits)
1124 pub const offset: u32 = 12;
1125 /// Mask (1 bit: 1 << 12)
1126 pub const mask: u32 = 1 << offset;
1127 /// Read-only values (empty)
1128 pub mod R {}
1129 /// Write-only values (empty)
1130 pub mod W {}
1131 /// Read-write values (empty)
1132 pub mod RW {}
1133 }
1134}
1135
1136/// I2S prescaler register
1137pub mod I2SPR {
1138
1139 /// Master clock output enable
1140 pub mod MCKOE {
1141 /// Offset (9 bits)
1142 pub const offset: u32 = 9;
1143 /// Mask (1 bit: 1 << 9)
1144 pub const mask: u32 = 1 << offset;
1145 /// Read-only values (empty)
1146 pub mod R {}
1147 /// Write-only values (empty)
1148 pub mod W {}
1149 /// Read-write values
1150 pub mod RW {
1151
1152 /// 0b0: Master clock output is disabled
1153 pub const Disabled: u32 = 0b0;
1154
1155 /// 0b1: Master clock output is enabled
1156 pub const Enabled: u32 = 0b1;
1157 }
1158 }
1159
1160 /// Odd factor for the prescaler
1161 pub mod ODD {
1162 /// Offset (8 bits)
1163 pub const offset: u32 = 8;
1164 /// Mask (1 bit: 1 << 8)
1165 pub const mask: u32 = 1 << offset;
1166 /// Read-only values (empty)
1167 pub mod R {}
1168 /// Write-only values (empty)
1169 pub mod W {}
1170 /// Read-write values
1171 pub mod RW {
1172
1173 /// 0b0: Real divider value is I2SDIV * 2
1174 pub const Even: u32 = 0b0;
1175
1176 /// 0b1: Real divider value is (I2SDIV * 2) + 1
1177 pub const Odd: u32 = 0b1;
1178 }
1179 }
1180
1181 /// I2S Linear prescaler
1182 pub mod I2SDIV {
1183 /// Offset (0 bits)
1184 pub const offset: u32 = 0;
1185 /// Mask (8 bits: 0xff << 0)
1186 pub const mask: u32 = 0xff << offset;
1187 /// Read-only values (empty)
1188 pub mod R {}
1189 /// Write-only values (empty)
1190 pub mod W {}
1191 /// Read-write values (empty)
1192 pub mod RW {}
1193 }
1194}
1195#[repr(C)]
1196pub struct RegisterBlock {
1197 /// control register 1
1198 pub CR1: RWRegister<u32>,
1199
1200 /// control register 2
1201 pub CR2: RWRegister<u32>,
1202
1203 /// status register
1204 pub SR: RWRegister<u32>,
1205
1206 /// data register
1207 pub DR: RWRegister<u32>,
1208
1209 /// CRC polynomial register
1210 pub CRCPR: RWRegister<u32>,
1211
1212 /// RX CRC register
1213 pub RXCRCR: RORegister<u32>,
1214
1215 /// TX CRC register
1216 pub TXCRCR: RORegister<u32>,
1217
1218 /// I2S configuration register
1219 pub I2SCFGR: RWRegister<u32>,
1220
1221 /// I2S prescaler register
1222 pub I2SPR: RWRegister<u32>,
1223}
1224pub struct ResetValues {
1225 pub CR1: u32,
1226 pub CR2: u32,
1227 pub SR: u32,
1228 pub DR: u32,
1229 pub CRCPR: u32,
1230 pub RXCRCR: u32,
1231 pub TXCRCR: u32,
1232 pub I2SCFGR: u32,
1233 pub I2SPR: u32,
1234}
1235#[cfg(not(feature = "nosync"))]
1236pub struct Instance {
1237 pub(crate) addr: u32,
1238 pub(crate) _marker: PhantomData<*const RegisterBlock>,
1239}
1240#[cfg(not(feature = "nosync"))]
1241impl ::core::ops::Deref for Instance {
1242 type Target = RegisterBlock;
1243 #[inline(always)]
1244 fn deref(&self) -> &RegisterBlock {
1245 unsafe { &*(self.addr as *const _) }
1246 }
1247}
1248#[cfg(feature = "rtic")]
1249unsafe impl Send for Instance {}