stm32ral/stm32f4/stm32f410/flash.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! FLASH
4
5use crate::{RWRegister, WORegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Flash access control register
10pub mod ACR {
11
12 /// Latency
13 pub mod LATENCY {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (4 bits: 0b1111 << 0)
17 pub const mask: u32 = 0b1111 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values
23 pub mod RW {
24
25 /// 0b0000: 0 wait states
26 pub const WS0: u32 = 0b0000;
27
28 /// 0b0001: 1 wait states
29 pub const WS1: u32 = 0b0001;
30
31 /// 0b0010: 2 wait states
32 pub const WS2: u32 = 0b0010;
33
34 /// 0b0011: 3 wait states
35 pub const WS3: u32 = 0b0011;
36
37 /// 0b0100: 4 wait states
38 pub const WS4: u32 = 0b0100;
39
40 /// 0b0101: 5 wait states
41 pub const WS5: u32 = 0b0101;
42
43 /// 0b0110: 6 wait states
44 pub const WS6: u32 = 0b0110;
45
46 /// 0b0111: 7 wait states
47 pub const WS7: u32 = 0b0111;
48
49 /// 0b1000: 8 wait states
50 pub const WS8: u32 = 0b1000;
51
52 /// 0b1001: 9 wait states
53 pub const WS9: u32 = 0b1001;
54
55 /// 0b1010: 10 wait states
56 pub const WS10: u32 = 0b1010;
57
58 /// 0b1011: 11 wait states
59 pub const WS11: u32 = 0b1011;
60
61 /// 0b1100: 12 wait states
62 pub const WS12: u32 = 0b1100;
63
64 /// 0b1101: 13 wait states
65 pub const WS13: u32 = 0b1101;
66
67 /// 0b1110: 14 wait states
68 pub const WS14: u32 = 0b1110;
69
70 /// 0b1111: 15 wait states
71 pub const WS15: u32 = 0b1111;
72 }
73 }
74
75 /// Prefetch enable
76 pub mod PRFTEN {
77 /// Offset (8 bits)
78 pub const offset: u32 = 8;
79 /// Mask (1 bit: 1 << 8)
80 pub const mask: u32 = 1 << offset;
81 /// Read-only values (empty)
82 pub mod R {}
83 /// Write-only values (empty)
84 pub mod W {}
85 /// Read-write values
86 pub mod RW {
87
88 /// 0b0: Prefetch is disabled
89 pub const Disabled: u32 = 0b0;
90
91 /// 0b1: Prefetch is enabled
92 pub const Enabled: u32 = 0b1;
93 }
94 }
95
96 /// Instruction cache enable
97 pub mod ICEN {
98 /// Offset (9 bits)
99 pub const offset: u32 = 9;
100 /// Mask (1 bit: 1 << 9)
101 pub const mask: u32 = 1 << offset;
102 /// Read-only values (empty)
103 pub mod R {}
104 /// Write-only values (empty)
105 pub mod W {}
106 /// Read-write values
107 pub mod RW {
108
109 /// 0b0: Instruction cache is disabled
110 pub const Disabled: u32 = 0b0;
111
112 /// 0b1: Instruction cache is enabled
113 pub const Enabled: u32 = 0b1;
114 }
115 }
116
117 /// Data cache enable
118 pub mod DCEN {
119 /// Offset (10 bits)
120 pub const offset: u32 = 10;
121 /// Mask (1 bit: 1 << 10)
122 pub const mask: u32 = 1 << offset;
123 /// Read-only values (empty)
124 pub mod R {}
125 /// Write-only values (empty)
126 pub mod W {}
127 /// Read-write values
128 pub mod RW {
129
130 /// 0b0: Data cache is disabled
131 pub const Disabled: u32 = 0b0;
132
133 /// 0b1: Data cache is enabled
134 pub const Enabled: u32 = 0b1;
135 }
136 }
137
138 /// Instruction cache reset
139 pub mod ICRST {
140 /// Offset (11 bits)
141 pub const offset: u32 = 11;
142 /// Mask (1 bit: 1 << 11)
143 pub const mask: u32 = 1 << offset;
144 /// Read-only values (empty)
145 pub mod R {}
146 /// Write-only values
147 pub mod W {
148
149 /// 0b0: Instruction cache is not reset
150 pub const NotReset: u32 = 0b0;
151
152 /// 0b1: Instruction cache is reset
153 pub const Reset: u32 = 0b1;
154 }
155 /// Read-write values (empty)
156 pub mod RW {}
157 }
158
159 /// Data cache reset
160 pub mod DCRST {
161 /// Offset (12 bits)
162 pub const offset: u32 = 12;
163 /// Mask (1 bit: 1 << 12)
164 pub const mask: u32 = 1 << offset;
165 /// Read-only values (empty)
166 pub mod R {}
167 /// Write-only values (empty)
168 pub mod W {}
169 /// Read-write values
170 pub mod RW {
171
172 /// 0b0: Data cache is not reset
173 pub const NotReset: u32 = 0b0;
174
175 /// 0b1: Data cache is reset
176 pub const Reset: u32 = 0b1;
177 }
178 }
179}
180
181/// Flash key register
182pub mod KEYR {
183
184 /// FPEC key
185 pub mod KEY {
186 /// Offset (0 bits)
187 pub const offset: u32 = 0;
188 /// Mask (32 bits: 0xffffffff << 0)
189 pub const mask: u32 = 0xffffffff << offset;
190 /// Read-only values (empty)
191 pub mod R {}
192 /// Write-only values (empty)
193 pub mod W {}
194 /// Read-write values (empty)
195 pub mod RW {}
196 }
197}
198
199/// Flash option key register
200pub mod OPTKEYR {
201
202 /// Option byte key
203 pub mod OPTKEY {
204 /// Offset (0 bits)
205 pub const offset: u32 = 0;
206 /// Mask (32 bits: 0xffffffff << 0)
207 pub const mask: u32 = 0xffffffff << offset;
208 /// Read-only values (empty)
209 pub mod R {}
210 /// Write-only values (empty)
211 pub mod W {}
212 /// Read-write values (empty)
213 pub mod RW {}
214 }
215}
216
217/// Status register
218pub mod SR {
219
220 /// End of operation
221 pub mod EOP {
222 /// Offset (0 bits)
223 pub const offset: u32 = 0;
224 /// Mask (1 bit: 1 << 0)
225 pub const mask: u32 = 1 << offset;
226 /// Read-only values (empty)
227 pub mod R {}
228 /// Write-only values (empty)
229 pub mod W {}
230 /// Read-write values (empty)
231 pub mod RW {}
232 }
233
234 /// Operation error
235 pub mod OPERR {
236 /// Offset (1 bits)
237 pub const offset: u32 = 1;
238 /// Mask (1 bit: 1 << 1)
239 pub const mask: u32 = 1 << offset;
240 /// Read-only values (empty)
241 pub mod R {}
242 /// Write-only values (empty)
243 pub mod W {}
244 /// Read-write values (empty)
245 pub mod RW {}
246 }
247
248 /// Write protection error
249 pub mod WRPERR {
250 /// Offset (4 bits)
251 pub const offset: u32 = 4;
252 /// Mask (1 bit: 1 << 4)
253 pub const mask: u32 = 1 << offset;
254 /// Read-only values (empty)
255 pub mod R {}
256 /// Write-only values (empty)
257 pub mod W {}
258 /// Read-write values (empty)
259 pub mod RW {}
260 }
261
262 /// Programming alignment error
263 pub mod PGAERR {
264 /// Offset (5 bits)
265 pub const offset: u32 = 5;
266 /// Mask (1 bit: 1 << 5)
267 pub const mask: u32 = 1 << offset;
268 /// Read-only values (empty)
269 pub mod R {}
270 /// Write-only values (empty)
271 pub mod W {}
272 /// Read-write values (empty)
273 pub mod RW {}
274 }
275
276 /// Programming parallelism error
277 pub mod PGPERR {
278 /// Offset (6 bits)
279 pub const offset: u32 = 6;
280 /// Mask (1 bit: 1 << 6)
281 pub const mask: u32 = 1 << offset;
282 /// Read-only values (empty)
283 pub mod R {}
284 /// Write-only values (empty)
285 pub mod W {}
286 /// Read-write values (empty)
287 pub mod RW {}
288 }
289
290 /// Programming sequence error
291 pub mod PGSERR {
292 /// Offset (7 bits)
293 pub const offset: u32 = 7;
294 /// Mask (1 bit: 1 << 7)
295 pub const mask: u32 = 1 << offset;
296 /// Read-only values (empty)
297 pub mod R {}
298 /// Write-only values (empty)
299 pub mod W {}
300 /// Read-write values (empty)
301 pub mod RW {}
302 }
303
304 /// Busy
305 pub mod BSY {
306 /// Offset (16 bits)
307 pub const offset: u32 = 16;
308 /// Mask (1 bit: 1 << 16)
309 pub const mask: u32 = 1 << offset;
310 /// Read-only values (empty)
311 pub mod R {}
312 /// Write-only values (empty)
313 pub mod W {}
314 /// Read-write values (empty)
315 pub mod RW {}
316 }
317}
318
319/// Control register
320pub mod CR {
321
322 /// Programming
323 pub mod PG {
324 /// Offset (0 bits)
325 pub const offset: u32 = 0;
326 /// Mask (1 bit: 1 << 0)
327 pub const mask: u32 = 1 << offset;
328 /// Read-only values (empty)
329 pub mod R {}
330 /// Write-only values (empty)
331 pub mod W {}
332 /// Read-write values
333 pub mod RW {
334
335 /// 0b1: Flash programming activated
336 pub const Program: u32 = 0b1;
337 }
338 }
339
340 /// Sector Erase
341 pub mod SER {
342 /// Offset (1 bits)
343 pub const offset: u32 = 1;
344 /// Mask (1 bit: 1 << 1)
345 pub const mask: u32 = 1 << offset;
346 /// Read-only values (empty)
347 pub mod R {}
348 /// Write-only values (empty)
349 pub mod W {}
350 /// Read-write values
351 pub mod RW {
352
353 /// 0b1: Erase activated for selected sector
354 pub const SectorErase: u32 = 0b1;
355 }
356 }
357
358 /// Mass Erase
359 pub mod MER {
360 /// Offset (2 bits)
361 pub const offset: u32 = 2;
362 /// Mask (1 bit: 1 << 2)
363 pub const mask: u32 = 1 << offset;
364 /// Read-only values (empty)
365 pub mod R {}
366 /// Write-only values (empty)
367 pub mod W {}
368 /// Read-write values
369 pub mod RW {
370
371 /// 0b1: Erase activated for all user sectors
372 pub const MassErase: u32 = 0b1;
373 }
374 }
375
376 /// Sector number
377 pub mod SNB {
378 /// Offset (3 bits)
379 pub const offset: u32 = 3;
380 /// Mask (4 bits: 0b1111 << 3)
381 pub const mask: u32 = 0b1111 << offset;
382 /// Read-only values (empty)
383 pub mod R {}
384 /// Write-only values (empty)
385 pub mod W {}
386 /// Read-write values (empty)
387 pub mod RW {}
388 }
389
390 /// Program size
391 pub mod PSIZE {
392 /// Offset (8 bits)
393 pub const offset: u32 = 8;
394 /// Mask (2 bits: 0b11 << 8)
395 pub const mask: u32 = 0b11 << offset;
396 /// Read-only values (empty)
397 pub mod R {}
398 /// Write-only values (empty)
399 pub mod W {}
400 /// Read-write values
401 pub mod RW {
402
403 /// 0b00: Program x8
404 pub const PSIZE8: u32 = 0b00;
405
406 /// 0b01: Program x16
407 pub const PSIZE16: u32 = 0b01;
408
409 /// 0b10: Program x32
410 pub const PSIZE32: u32 = 0b10;
411
412 /// 0b11: Program x64
413 pub const PSIZE64: u32 = 0b11;
414 }
415 }
416
417 /// Start
418 pub mod STRT {
419 /// Offset (16 bits)
420 pub const offset: u32 = 16;
421 /// Mask (1 bit: 1 << 16)
422 pub const mask: u32 = 1 << offset;
423 /// Read-only values (empty)
424 pub mod R {}
425 /// Write-only values (empty)
426 pub mod W {}
427 /// Read-write values
428 pub mod RW {
429
430 /// 0b1: Trigger an erase operation
431 pub const Start: u32 = 0b1;
432 }
433 }
434
435 /// End of operation interrupt enable
436 pub mod EOPIE {
437 /// Offset (24 bits)
438 pub const offset: u32 = 24;
439 /// Mask (1 bit: 1 << 24)
440 pub const mask: u32 = 1 << offset;
441 /// Read-only values (empty)
442 pub mod R {}
443 /// Write-only values (empty)
444 pub mod W {}
445 /// Read-write values
446 pub mod RW {
447
448 /// 0b0: End of operation interrupt disabled
449 pub const Disabled: u32 = 0b0;
450
451 /// 0b1: End of operation interrupt enabled
452 pub const Enabled: u32 = 0b1;
453 }
454 }
455
456 /// Error interrupt enable
457 pub mod ERRIE {
458 /// Offset (25 bits)
459 pub const offset: u32 = 25;
460 /// Mask (1 bit: 1 << 25)
461 pub const mask: u32 = 1 << offset;
462 /// Read-only values (empty)
463 pub mod R {}
464 /// Write-only values (empty)
465 pub mod W {}
466 /// Read-write values
467 pub mod RW {
468
469 /// 0b0: Error interrupt generation disabled
470 pub const Disabled: u32 = 0b0;
471
472 /// 0b1: Error interrupt generation enabled
473 pub const Enabled: u32 = 0b1;
474 }
475 }
476
477 /// Lock
478 pub mod LOCK {
479 /// Offset (31 bits)
480 pub const offset: u32 = 31;
481 /// Mask (1 bit: 1 << 31)
482 pub const mask: u32 = 1 << offset;
483 /// Read-only values (empty)
484 pub mod R {}
485 /// Write-only values (empty)
486 pub mod W {}
487 /// Read-write values
488 pub mod RW {
489
490 /// 0b0: FLASH_CR register is unlocked
491 pub const Unlocked: u32 = 0b0;
492
493 /// 0b1: FLASH_CR register is locked
494 pub const Locked: u32 = 0b1;
495 }
496 }
497}
498
499/// Flash option control register
500pub mod OPTCR {
501
502 /// Option lock
503 pub mod OPTLOCK {
504 /// Offset (0 bits)
505 pub const offset: u32 = 0;
506 /// Mask (1 bit: 1 << 0)
507 pub const mask: u32 = 1 << offset;
508 /// Read-only values (empty)
509 pub mod R {}
510 /// Write-only values (empty)
511 pub mod W {}
512 /// Read-write values (empty)
513 pub mod RW {}
514 }
515
516 /// Option start
517 pub mod OPTSTRT {
518 /// Offset (1 bits)
519 pub const offset: u32 = 1;
520 /// Mask (1 bit: 1 << 1)
521 pub const mask: u32 = 1 << offset;
522 /// Read-only values (empty)
523 pub mod R {}
524 /// Write-only values (empty)
525 pub mod W {}
526 /// Read-write values (empty)
527 pub mod RW {}
528 }
529
530 /// BOR reset Level
531 pub mod BOR_LEV {
532 /// Offset (2 bits)
533 pub const offset: u32 = 2;
534 /// Mask (2 bits: 0b11 << 2)
535 pub const mask: u32 = 0b11 << offset;
536 /// Read-only values (empty)
537 pub mod R {}
538 /// Write-only values (empty)
539 pub mod W {}
540 /// Read-write values (empty)
541 pub mod RW {}
542 }
543
544 /// WDG_SW User option bytes
545 pub mod WDG_SW {
546 /// Offset (5 bits)
547 pub const offset: u32 = 5;
548 /// Mask (1 bit: 1 << 5)
549 pub const mask: u32 = 1 << offset;
550 /// Read-only values (empty)
551 pub mod R {}
552 /// Write-only values (empty)
553 pub mod W {}
554 /// Read-write values (empty)
555 pub mod RW {}
556 }
557
558 /// nRST_STOP User option bytes
559 pub mod nRST_STOP {
560 /// Offset (6 bits)
561 pub const offset: u32 = 6;
562 /// Mask (1 bit: 1 << 6)
563 pub const mask: u32 = 1 << offset;
564 /// Read-only values (empty)
565 pub mod R {}
566 /// Write-only values (empty)
567 pub mod W {}
568 /// Read-write values (empty)
569 pub mod RW {}
570 }
571
572 /// nRST_STDBY User option bytes
573 pub mod nRST_STDBY {
574 /// Offset (7 bits)
575 pub const offset: u32 = 7;
576 /// Mask (1 bit: 1 << 7)
577 pub const mask: u32 = 1 << offset;
578 /// Read-only values (empty)
579 pub mod R {}
580 /// Write-only values (empty)
581 pub mod W {}
582 /// Read-write values (empty)
583 pub mod RW {}
584 }
585
586 /// Read protect
587 pub mod RDP {
588 /// Offset (8 bits)
589 pub const offset: u32 = 8;
590 /// Mask (8 bits: 0xff << 8)
591 pub const mask: u32 = 0xff << offset;
592 /// Read-only values (empty)
593 pub mod R {}
594 /// Write-only values (empty)
595 pub mod W {}
596 /// Read-write values (empty)
597 pub mod RW {}
598 }
599
600 /// Not write protect
601 pub mod nWRP {
602 /// Offset (16 bits)
603 pub const offset: u32 = 16;
604 /// Mask (5 bits: 0b11111 << 16)
605 pub const mask: u32 = 0b11111 << offset;
606 /// Read-only values (empty)
607 pub mod R {}
608 /// Write-only values (empty)
609 pub mod W {}
610 /// Read-write values (empty)
611 pub mod RW {}
612 }
613
614 /// SPRMOD
615 pub mod SPRMOD {
616 /// Offset (31 bits)
617 pub const offset: u32 = 31;
618 /// Mask (1 bit: 1 << 31)
619 pub const mask: u32 = 1 << offset;
620 /// Read-only values (empty)
621 pub mod R {}
622 /// Write-only values (empty)
623 pub mod W {}
624 /// Read-write values (empty)
625 pub mod RW {}
626 }
627}
628#[repr(C)]
629pub struct RegisterBlock {
630 /// Flash access control register
631 pub ACR: RWRegister<u32>,
632
633 /// Flash key register
634 pub KEYR: WORegister<u32>,
635
636 /// Flash option key register
637 pub OPTKEYR: WORegister<u32>,
638
639 /// Status register
640 pub SR: RWRegister<u32>,
641
642 /// Control register
643 pub CR: RWRegister<u32>,
644
645 /// Flash option control register
646 pub OPTCR: RWRegister<u32>,
647}
648pub struct ResetValues {
649 pub ACR: u32,
650 pub KEYR: u32,
651 pub OPTKEYR: u32,
652 pub SR: u32,
653 pub CR: u32,
654 pub OPTCR: u32,
655}
656#[cfg(not(feature = "nosync"))]
657pub struct Instance {
658 pub(crate) addr: u32,
659 pub(crate) _marker: PhantomData<*const RegisterBlock>,
660}
661#[cfg(not(feature = "nosync"))]
662impl ::core::ops::Deref for Instance {
663 type Target = RegisterBlock;
664 #[inline(always)]
665 fn deref(&self) -> &RegisterBlock {
666 unsafe { &*(self.addr as *const _) }
667 }
668}
669#[cfg(feature = "rtic")]
670unsafe impl Send for Instance {}
671
672/// Access functions for the FLASH peripheral instance
673pub mod FLASH {
674 use super::ResetValues;
675
676 #[cfg(not(feature = "nosync"))]
677 use super::Instance;
678
679 #[cfg(not(feature = "nosync"))]
680 const INSTANCE: Instance = Instance {
681 addr: 0x40023c00,
682 _marker: ::core::marker::PhantomData,
683 };
684
685 /// Reset values for each field in FLASH
686 pub const reset: ResetValues = ResetValues {
687 ACR: 0x00000000,
688 KEYR: 0x00000000,
689 OPTKEYR: 0x00000000,
690 SR: 0x00000000,
691 CR: 0x80000000,
692 OPTCR: 0x7FFFAAED,
693 };
694
695 #[cfg(not(feature = "nosync"))]
696 #[allow(renamed_and_removed_lints)]
697 #[allow(private_no_mangle_statics)]
698 #[no_mangle]
699 static mut FLASH_TAKEN: bool = false;
700
701 /// Safe access to FLASH
702 ///
703 /// This function returns `Some(Instance)` if this instance is not
704 /// currently taken, and `None` if it is. This ensures that if you
705 /// do get `Some(Instance)`, you are ensured unique access to
706 /// the peripheral and there cannot be data races (unless other
707 /// code uses `unsafe`, of course). You can then pass the
708 /// `Instance` around to other functions as required. When you're
709 /// done with it, you can call `release(instance)` to return it.
710 ///
711 /// `Instance` itself dereferences to a `RegisterBlock`, which
712 /// provides access to the peripheral's registers.
713 #[cfg(not(feature = "nosync"))]
714 #[inline]
715 pub fn take() -> Option<Instance> {
716 external_cortex_m::interrupt::free(|_| unsafe {
717 if FLASH_TAKEN {
718 None
719 } else {
720 FLASH_TAKEN = true;
721 Some(INSTANCE)
722 }
723 })
724 }
725
726 /// Release exclusive access to FLASH
727 ///
728 /// This function allows you to return an `Instance` so that it
729 /// is available to `take()` again. This function will panic if
730 /// you return a different `Instance` or if this instance is not
731 /// already taken.
732 #[cfg(not(feature = "nosync"))]
733 #[inline]
734 pub fn release(inst: Instance) {
735 external_cortex_m::interrupt::free(|_| unsafe {
736 if FLASH_TAKEN && inst.addr == INSTANCE.addr {
737 FLASH_TAKEN = false;
738 } else {
739 panic!("Released a peripheral which was not taken");
740 }
741 });
742 }
743
744 /// Unsafely steal FLASH
745 ///
746 /// This function is similar to take() but forcibly takes the
747 /// Instance, marking it as taken irregardless of its previous
748 /// state.
749 #[cfg(not(feature = "nosync"))]
750 #[inline]
751 pub unsafe fn steal() -> Instance {
752 FLASH_TAKEN = true;
753 INSTANCE
754 }
755}
756
757/// Raw pointer to FLASH
758///
759/// Dereferencing this is unsafe because you are not ensured unique
760/// access to the peripheral, so you may encounter data races with
761/// other users of this peripheral. It is up to you to ensure you
762/// will not cause data races.
763///
764/// This constant is provided for ease of use in unsafe code: you can
765/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
766pub const FLASH: *const RegisterBlock = 0x40023c00 as *const _;