stm32ral/stm32f4/stm32f405/ethernet_mmc.rs
1#![allow(non_snake_case, non_upper_case_globals)]
2#![allow(non_camel_case_types)]
3//! Ethernet: MAC management counters
4
5use crate::{RORegister, RWRegister};
6#[cfg(not(feature = "nosync"))]
7use core::marker::PhantomData;
8
9/// Ethernet MMC control register
10pub mod MMCCR {
11
12 /// CR
13 pub mod CR {
14 /// Offset (0 bits)
15 pub const offset: u32 = 0;
16 /// Mask (1 bit: 1 << 0)
17 pub const mask: u32 = 1 << offset;
18 /// Read-only values (empty)
19 pub mod R {}
20 /// Write-only values (empty)
21 pub mod W {}
22 /// Read-write values (empty)
23 pub mod RW {}
24 }
25
26 /// CSR
27 pub mod CSR {
28 /// Offset (1 bits)
29 pub const offset: u32 = 1;
30 /// Mask (1 bit: 1 << 1)
31 pub const mask: u32 = 1 << offset;
32 /// Read-only values (empty)
33 pub mod R {}
34 /// Write-only values (empty)
35 pub mod W {}
36 /// Read-write values (empty)
37 pub mod RW {}
38 }
39
40 /// ROR
41 pub mod ROR {
42 /// Offset (2 bits)
43 pub const offset: u32 = 2;
44 /// Mask (1 bit: 1 << 2)
45 pub const mask: u32 = 1 << offset;
46 /// Read-only values (empty)
47 pub mod R {}
48 /// Write-only values (empty)
49 pub mod W {}
50 /// Read-write values (empty)
51 pub mod RW {}
52 }
53
54 /// MCF
55 pub mod MCF {
56 /// Offset (3 bits)
57 pub const offset: u32 = 3;
58 /// Mask (1 bit: 1 << 3)
59 pub const mask: u32 = 1 << offset;
60 /// Read-only values (empty)
61 pub mod R {}
62 /// Write-only values (empty)
63 pub mod W {}
64 /// Read-write values (empty)
65 pub mod RW {}
66 }
67
68 /// MCP
69 pub mod MCP {
70 /// Offset (4 bits)
71 pub const offset: u32 = 4;
72 /// Mask (1 bit: 1 << 4)
73 pub const mask: u32 = 1 << offset;
74 /// Read-only values (empty)
75 pub mod R {}
76 /// Write-only values (empty)
77 pub mod W {}
78 /// Read-write values (empty)
79 pub mod RW {}
80 }
81
82 /// MCFHP
83 pub mod MCFHP {
84 /// Offset (5 bits)
85 pub const offset: u32 = 5;
86 /// Mask (1 bit: 1 << 5)
87 pub const mask: u32 = 1 << offset;
88 /// Read-only values (empty)
89 pub mod R {}
90 /// Write-only values (empty)
91 pub mod W {}
92 /// Read-write values (empty)
93 pub mod RW {}
94 }
95}
96
97/// Ethernet MMC receive interrupt register
98pub mod MMCRIR {
99
100 /// RFCES
101 pub mod RFCES {
102 /// Offset (5 bits)
103 pub const offset: u32 = 5;
104 /// Mask (1 bit: 1 << 5)
105 pub const mask: u32 = 1 << offset;
106 /// Read-only values (empty)
107 pub mod R {}
108 /// Write-only values (empty)
109 pub mod W {}
110 /// Read-write values (empty)
111 pub mod RW {}
112 }
113
114 /// RFAES
115 pub mod RFAES {
116 /// Offset (6 bits)
117 pub const offset: u32 = 6;
118 /// Mask (1 bit: 1 << 6)
119 pub const mask: u32 = 1 << offset;
120 /// Read-only values (empty)
121 pub mod R {}
122 /// Write-only values (empty)
123 pub mod W {}
124 /// Read-write values (empty)
125 pub mod RW {}
126 }
127
128 /// RGUFS
129 pub mod RGUFS {
130 /// Offset (17 bits)
131 pub const offset: u32 = 17;
132 /// Mask (1 bit: 1 << 17)
133 pub const mask: u32 = 1 << offset;
134 /// Read-only values (empty)
135 pub mod R {}
136 /// Write-only values (empty)
137 pub mod W {}
138 /// Read-write values (empty)
139 pub mod RW {}
140 }
141}
142
143/// Ethernet MMC transmit interrupt register
144pub mod MMCTIR {
145
146 /// TGFSCS
147 pub mod TGFSCS {
148 /// Offset (14 bits)
149 pub const offset: u32 = 14;
150 /// Mask (1 bit: 1 << 14)
151 pub const mask: u32 = 1 << offset;
152 /// Read-only values (empty)
153 pub mod R {}
154 /// Write-only values (empty)
155 pub mod W {}
156 /// Read-write values (empty)
157 pub mod RW {}
158 }
159
160 /// TGFMSCS
161 pub mod TGFMSCS {
162 /// Offset (15 bits)
163 pub const offset: u32 = 15;
164 /// Mask (1 bit: 1 << 15)
165 pub const mask: u32 = 1 << offset;
166 /// Read-only values (empty)
167 pub mod R {}
168 /// Write-only values (empty)
169 pub mod W {}
170 /// Read-write values (empty)
171 pub mod RW {}
172 }
173
174 /// TGFS
175 pub mod TGFS {
176 /// Offset (21 bits)
177 pub const offset: u32 = 21;
178 /// Mask (1 bit: 1 << 21)
179 pub const mask: u32 = 1 << offset;
180 /// Read-only values (empty)
181 pub mod R {}
182 /// Write-only values (empty)
183 pub mod W {}
184 /// Read-write values (empty)
185 pub mod RW {}
186 }
187}
188
189/// Ethernet MMC receive interrupt mask register
190pub mod MMCRIMR {
191
192 /// RFCEM
193 pub mod RFCEM {
194 /// Offset (5 bits)
195 pub const offset: u32 = 5;
196 /// Mask (1 bit: 1 << 5)
197 pub const mask: u32 = 1 << offset;
198 /// Read-only values (empty)
199 pub mod R {}
200 /// Write-only values (empty)
201 pub mod W {}
202 /// Read-write values (empty)
203 pub mod RW {}
204 }
205
206 /// RFAEM
207 pub mod RFAEM {
208 /// Offset (6 bits)
209 pub const offset: u32 = 6;
210 /// Mask (1 bit: 1 << 6)
211 pub const mask: u32 = 1 << offset;
212 /// Read-only values (empty)
213 pub mod R {}
214 /// Write-only values (empty)
215 pub mod W {}
216 /// Read-write values (empty)
217 pub mod RW {}
218 }
219
220 /// RGUFM
221 pub mod RGUFM {
222 /// Offset (17 bits)
223 pub const offset: u32 = 17;
224 /// Mask (1 bit: 1 << 17)
225 pub const mask: u32 = 1 << offset;
226 /// Read-only values (empty)
227 pub mod R {}
228 /// Write-only values (empty)
229 pub mod W {}
230 /// Read-write values (empty)
231 pub mod RW {}
232 }
233}
234
235/// Ethernet MMC transmit interrupt mask register
236pub mod MMCTIMR {
237
238 /// TGFSCM
239 pub mod TGFSCM {
240 /// Offset (14 bits)
241 pub const offset: u32 = 14;
242 /// Mask (1 bit: 1 << 14)
243 pub const mask: u32 = 1 << offset;
244 /// Read-only values (empty)
245 pub mod R {}
246 /// Write-only values (empty)
247 pub mod W {}
248 /// Read-write values (empty)
249 pub mod RW {}
250 }
251
252 /// TGFMSCM
253 pub mod TGFMSCM {
254 /// Offset (15 bits)
255 pub const offset: u32 = 15;
256 /// Mask (1 bit: 1 << 15)
257 pub const mask: u32 = 1 << offset;
258 /// Read-only values (empty)
259 pub mod R {}
260 /// Write-only values (empty)
261 pub mod W {}
262 /// Read-write values (empty)
263 pub mod RW {}
264 }
265
266 /// TGFM
267 pub mod TGFM {
268 /// Offset (16 bits)
269 pub const offset: u32 = 16;
270 /// Mask (1 bit: 1 << 16)
271 pub const mask: u32 = 1 << offset;
272 /// Read-only values (empty)
273 pub mod R {}
274 /// Write-only values (empty)
275 pub mod W {}
276 /// Read-write values (empty)
277 pub mod RW {}
278 }
279}
280
281/// Ethernet MMC transmitted good frames after a single collision counter
282pub mod MMCTGFSCCR {
283
284 /// TGFSCC
285 pub mod TGFSCC {
286 /// Offset (0 bits)
287 pub const offset: u32 = 0;
288 /// Mask (32 bits: 0xffffffff << 0)
289 pub const mask: u32 = 0xffffffff << offset;
290 /// Read-only values (empty)
291 pub mod R {}
292 /// Write-only values (empty)
293 pub mod W {}
294 /// Read-write values (empty)
295 pub mod RW {}
296 }
297}
298
299/// Ethernet MMC transmitted good frames after more than a single collision
300pub mod MMCTGFMSCCR {
301
302 /// TGFMSCC
303 pub mod TGFMSCC {
304 /// Offset (0 bits)
305 pub const offset: u32 = 0;
306 /// Mask (32 bits: 0xffffffff << 0)
307 pub const mask: u32 = 0xffffffff << offset;
308 /// Read-only values (empty)
309 pub mod R {}
310 /// Write-only values (empty)
311 pub mod W {}
312 /// Read-write values (empty)
313 pub mod RW {}
314 }
315}
316
317/// Ethernet MMC transmitted good frames counter register
318pub mod MMCTGFCR {
319
320 /// HTL
321 pub mod TGFC {
322 /// Offset (0 bits)
323 pub const offset: u32 = 0;
324 /// Mask (32 bits: 0xffffffff << 0)
325 pub const mask: u32 = 0xffffffff << offset;
326 /// Read-only values (empty)
327 pub mod R {}
328 /// Write-only values (empty)
329 pub mod W {}
330 /// Read-write values (empty)
331 pub mod RW {}
332 }
333}
334
335/// Ethernet MMC received frames with CRC error counter register
336pub mod MMCRFCECR {
337
338 /// RFCFC
339 pub mod RFCFC {
340 /// Offset (0 bits)
341 pub const offset: u32 = 0;
342 /// Mask (32 bits: 0xffffffff << 0)
343 pub const mask: u32 = 0xffffffff << offset;
344 /// Read-only values (empty)
345 pub mod R {}
346 /// Write-only values (empty)
347 pub mod W {}
348 /// Read-write values (empty)
349 pub mod RW {}
350 }
351}
352
353/// Ethernet MMC received frames with alignment error counter register
354pub mod MMCRFAECR {
355
356 /// RFAEC
357 pub mod RFAEC {
358 /// Offset (0 bits)
359 pub const offset: u32 = 0;
360 /// Mask (32 bits: 0xffffffff << 0)
361 pub const mask: u32 = 0xffffffff << offset;
362 /// Read-only values (empty)
363 pub mod R {}
364 /// Write-only values (empty)
365 pub mod W {}
366 /// Read-write values (empty)
367 pub mod RW {}
368 }
369}
370
371/// MMC received good unicast frames counter register
372pub mod MMCRGUFCR {
373
374 /// RGUFC
375 pub mod RGUFC {
376 /// Offset (0 bits)
377 pub const offset: u32 = 0;
378 /// Mask (32 bits: 0xffffffff << 0)
379 pub const mask: u32 = 0xffffffff << offset;
380 /// Read-only values (empty)
381 pub mod R {}
382 /// Write-only values (empty)
383 pub mod W {}
384 /// Read-write values (empty)
385 pub mod RW {}
386 }
387}
388#[repr(C)]
389pub struct RegisterBlock {
390 /// Ethernet MMC control register
391 pub MMCCR: RWRegister<u32>,
392
393 /// Ethernet MMC receive interrupt register
394 pub MMCRIR: RWRegister<u32>,
395
396 /// Ethernet MMC transmit interrupt register
397 pub MMCTIR: RORegister<u32>,
398
399 /// Ethernet MMC receive interrupt mask register
400 pub MMCRIMR: RWRegister<u32>,
401
402 /// Ethernet MMC transmit interrupt mask register
403 pub MMCTIMR: RWRegister<u32>,
404
405 _reserved1: [u8; 56],
406
407 /// Ethernet MMC transmitted good frames after a single collision counter
408 pub MMCTGFSCCR: RORegister<u32>,
409
410 /// Ethernet MMC transmitted good frames after more than a single collision
411 pub MMCTGFMSCCR: RORegister<u32>,
412
413 _reserved2: [u8; 20],
414
415 /// Ethernet MMC transmitted good frames counter register
416 pub MMCTGFCR: RORegister<u32>,
417
418 _reserved3: [u8; 40],
419
420 /// Ethernet MMC received frames with CRC error counter register
421 pub MMCRFCECR: RORegister<u32>,
422
423 /// Ethernet MMC received frames with alignment error counter register
424 pub MMCRFAECR: RORegister<u32>,
425
426 _reserved4: [u8; 40],
427
428 /// MMC received good unicast frames counter register
429 pub MMCRGUFCR: RORegister<u32>,
430}
431pub struct ResetValues {
432 pub MMCCR: u32,
433 pub MMCRIR: u32,
434 pub MMCTIR: u32,
435 pub MMCRIMR: u32,
436 pub MMCTIMR: u32,
437 pub MMCTGFSCCR: u32,
438 pub MMCTGFMSCCR: u32,
439 pub MMCTGFCR: u32,
440 pub MMCRFCECR: u32,
441 pub MMCRFAECR: u32,
442 pub MMCRGUFCR: u32,
443}
444#[cfg(not(feature = "nosync"))]
445pub struct Instance {
446 pub(crate) addr: u32,
447 pub(crate) _marker: PhantomData<*const RegisterBlock>,
448}
449#[cfg(not(feature = "nosync"))]
450impl ::core::ops::Deref for Instance {
451 type Target = RegisterBlock;
452 #[inline(always)]
453 fn deref(&self) -> &RegisterBlock {
454 unsafe { &*(self.addr as *const _) }
455 }
456}
457#[cfg(feature = "rtic")]
458unsafe impl Send for Instance {}
459
460/// Access functions for the Ethernet_MMC peripheral instance
461pub mod Ethernet_MMC {
462 use super::ResetValues;
463
464 #[cfg(not(feature = "nosync"))]
465 use super::Instance;
466
467 #[cfg(not(feature = "nosync"))]
468 const INSTANCE: Instance = Instance {
469 addr: 0x40028100,
470 _marker: ::core::marker::PhantomData,
471 };
472
473 /// Reset values for each field in Ethernet_MMC
474 pub const reset: ResetValues = ResetValues {
475 MMCCR: 0x00000000,
476 MMCRIR: 0x00000000,
477 MMCTIR: 0x00000000,
478 MMCRIMR: 0x00000000,
479 MMCTIMR: 0x00000000,
480 MMCTGFSCCR: 0x00000000,
481 MMCTGFMSCCR: 0x00000000,
482 MMCTGFCR: 0x00000000,
483 MMCRFCECR: 0x00000000,
484 MMCRFAECR: 0x00000000,
485 MMCRGUFCR: 0x00000000,
486 };
487
488 #[cfg(not(feature = "nosync"))]
489 #[allow(renamed_and_removed_lints)]
490 #[allow(private_no_mangle_statics)]
491 #[no_mangle]
492 static mut Ethernet_MMC_TAKEN: bool = false;
493
494 /// Safe access to Ethernet_MMC
495 ///
496 /// This function returns `Some(Instance)` if this instance is not
497 /// currently taken, and `None` if it is. This ensures that if you
498 /// do get `Some(Instance)`, you are ensured unique access to
499 /// the peripheral and there cannot be data races (unless other
500 /// code uses `unsafe`, of course). You can then pass the
501 /// `Instance` around to other functions as required. When you're
502 /// done with it, you can call `release(instance)` to return it.
503 ///
504 /// `Instance` itself dereferences to a `RegisterBlock`, which
505 /// provides access to the peripheral's registers.
506 #[cfg(not(feature = "nosync"))]
507 #[inline]
508 pub fn take() -> Option<Instance> {
509 external_cortex_m::interrupt::free(|_| unsafe {
510 if Ethernet_MMC_TAKEN {
511 None
512 } else {
513 Ethernet_MMC_TAKEN = true;
514 Some(INSTANCE)
515 }
516 })
517 }
518
519 /// Release exclusive access to Ethernet_MMC
520 ///
521 /// This function allows you to return an `Instance` so that it
522 /// is available to `take()` again. This function will panic if
523 /// you return a different `Instance` or if this instance is not
524 /// already taken.
525 #[cfg(not(feature = "nosync"))]
526 #[inline]
527 pub fn release(inst: Instance) {
528 external_cortex_m::interrupt::free(|_| unsafe {
529 if Ethernet_MMC_TAKEN && inst.addr == INSTANCE.addr {
530 Ethernet_MMC_TAKEN = false;
531 } else {
532 panic!("Released a peripheral which was not taken");
533 }
534 });
535 }
536
537 /// Unsafely steal Ethernet_MMC
538 ///
539 /// This function is similar to take() but forcibly takes the
540 /// Instance, marking it as taken irregardless of its previous
541 /// state.
542 #[cfg(not(feature = "nosync"))]
543 #[inline]
544 pub unsafe fn steal() -> Instance {
545 Ethernet_MMC_TAKEN = true;
546 INSTANCE
547 }
548}
549
550/// Raw pointer to Ethernet_MMC
551///
552/// Dereferencing this is unsafe because you are not ensured unique
553/// access to the peripheral, so you may encounter data races with
554/// other users of this peripheral. It is up to you to ensure you
555/// will not cause data races.
556///
557/// This constant is provided for ease of use in unsafe code: you can
558/// simply call for example `write_reg!(gpio, GPIOA, ODR, 1);`.
559pub const Ethernet_MMC: *const RegisterBlock = 0x40028100 as *const _;